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| DC ELECTRICAL CHARACTERISTICS |
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| PARAMETER | SYMBOL | CONDITION | MIN | TYP |
| MAX | UNITS |
| NOTES |
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| Input Leakage (SDA, | ILI |
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| +1 | μA | 2 |
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| SCL) |
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| Input Logic 1 (SDA, | VIH |
| 0.7Vcc |
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| Vcc+0.5 | V | 1 |
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| SCL) |
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| Input Logic 0 (SDA, | VIL |
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| 0.3Vcc | V | 1 |
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| SCL) |
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| Low Level Output | IOL1 | 0.4V | 3 |
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| mA | 1 |
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| Current (SDA) | IOL2 | 0.6V | 6 |
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| mA | 1 |
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| AC ELECTRICAL CHARACTERISTICS |
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| PARAMETER | SYMBOL | CONDITION | MIN | TYP |
| MAX | UNITS |
| NOTES |
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| SCL clock frequency | fSCL |
| 0 |
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| 400 | kHz |
| *,3 |
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| 0 |
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| 100 |
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| Bus free time between | tBUF |
| 1.3 |
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| μs |
| *,3 |
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| STOP and START |
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| 4.7 |
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| condition |
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| Hold time (repeated) | tHD:STA |
| 0.6 |
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| μs |
| *,3,4 |
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| START condition |
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| 4.0 |
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| Low period of SCL | tLOW |
| 1.3 |
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| μs |
| *,3 |
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| clock |
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| 4.7 |
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| High period of SCL | tHIGH |
| 0.6 |
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| μs |
| *,3 |
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| clock |
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| 4.0 |
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| Data hold time | tHD:DAT |
| 0 |
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| 0.9 | μs |
| *,3,5,6 |
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| 0 |
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| Data | tSU:DAT |
| 100 |
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| ns |
| *,3 |
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| 250 |
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| Start | tSU:STA |
| 0.6 |
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| μs |
| *,3 |
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| 4.7 |
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| Rise time of both SDA | tR |
| 20+0.1CB |
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| 300 | ns |
| * |
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| and SCL signals |
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| 1000 |
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| Fall time of both SDA | tF |
| 20+0.1CB |
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| 300 | ns |
| * |
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| and SCL signals |
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| 300 |
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| tSU:STO |
| 0.6 |
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| μs |
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| condition |
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| 4.0 |
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| Capacitive load for | CB |
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| 400 | pF |
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| each bus line |
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| EEPROM write time | TW |
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| 10 |
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*Fast mode
**Standard mode
Notes
1.All voltages are referenced to ground.
2.Input levels equal either Vcc or GND.
3.The output must be configured to source.
4.The output must be configured to have
5.This is the time for one comparison. The cycle is multiplied by 3.
6.This parameter is measured with maximum output current.
9/26/02 Revision D | Page 34 |