2System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the PCI Bus

The three DMA modes allow the following transfer rates:

Mode

0

1

2

 

 

 

 

Cycle time (ns)

480

150

120

 

 

 

 

Transfer rate (MBytes/s)

4.2

13.3

16.7

 

 

 

 

Operated in slave mode, the IDE controller saturates the PCI bus with transfers, thus limiting the actual achieved transfer rate to less than 10 MBytes per second.

Operated in master mode, though, the IDE controller is allowed to work autonomously of the processor, and the full 16.7 MBytes per second transfer rate can be achieved with less than 33% occupancy of the PCI bus (thus allowing the processor to do other work for more than 67% of the cycle times, while the IDE transfers take place in parallel).

Disk Capacity Versus Modes of Addressing

The amount of addressable space on the hard disk is limited by three factors:

•Physical size of the hard disk.

•Addressing limit of the IDE hardware.

•Addressing limit of the BIOS.

The Extended-CHS (Cylinder Header Sector) addressing scheme allows larger disk capacities to be addressed than under CHS, by performing a translation (for example regrouping the sectors so that there are twice as many logical tracks as is possible under the CHS addressing scheme).

 

Cylinders

Heads per

Sectors per

Bytes per

Bytes per

 

per Device

Cylinder

Track

Sector

Device

 

 

 

 

 

 

 

CHS

64

16

1024

512

528

M

 

 

 

 

 

 

 

ECHS

64

256

1024

512

8.4

G

 

 

 

 

 

 

LBA

-

-

256 M (=228)

512

137 G

If the Setup field has been set to automatic, the logical block addressing (LBA) mode will be selected for each device that supports it.

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