IBM 272 PC Processors (Mobile Celeron)

PC Processors (Mobile Celeron) - Fall 2001

Vendor

Positioning

Instruction architecture

MMX™ / Streaming SIMD

L1 cache - size

L1 cache - write policy

L1 cache - organization

L1 cache - bus

L1 cache - parity

L2 cache - size

L2 cache - data path

L2 cache - buffering

L2 cache - organization

L2 cache - controller

L2 cache - write policy

L2 cache - type

System bus - parity

System bus - speed

System bus - features

Bus architecture

Execution units

Pipeline stages

Supscal dispatch/execute

Superscalar issue

Superscalar retire

Out-of-order instructions

Branch prediction

Speculative execution

Math coprocessor

Internal processing

External data bus

External address bus

User registers

Cache line size

Power management

Multiple processors

Technology (micron)

CPU voltage

Package type

Frequency (available)

All trademarks are the property of their respective owners

(20INTEL) Compiled by Roger Dodson, IBM. January 2003

Intel®

Value mobile PC

IA-32 / P6 microarchitecture / CISC/RISC/micro-ops

MMX (57 new instructions) /

Streaming SIMD Extensions (70 new instructions)

16KB data; 16KB instruction

Write-back or thru (data); write-thru (instruction)

4-way set associative

64-bit / full speed / non-blocking

Parity in cache and internal registers

128KB / full speed

64-bit data path / ECC

8-way set associative / non-blocking

Integrated / unified (internal die; on die)

Write-through or write-back (programmable per line),

uncacheable, write-protect

ECC on system bus; parity on address bus (frontside)

133MHz frontside bus

Nonblocking cache hierarchy

Independent backside and frontside buses operate

concurrently / Dual Independent Bus Architecture

2 integer/MMX units; 1 floating pt unit;1 load unit; 1 store unit

Decoupled, 14 stage superpipelined

5 micro-ops per cycle (3 micro-ops is typical)

6 micro-ops per cycle (3 micro-ops is typical)

3 micro-ops per cycle

Yes (called dynamic execution)

Dynamic (based on history) / 512 entry BTB

Yes

Pipelined math coprocessor

32-bits (300 bit internal bus width) / 32-bit word size

64-bit system bus with ECC

36-bits (64GB physical address space; 64TB virtual)

8 GPR, 8 FP, 40 more GPR via register renaming

32 bytes (8 bytes x 4 chunks)

Quick Start and Deep Sleep

No SMP support

0.18u

1.7 volts

Micro-Flip Chip Ball Grid Array (Micro-FCBGA)

Micro-Flip Chip Pin Grid Array (Micro-FCPGA)

733MHz (October 2001)

800A MHz (October 2001)

866MHz (October 2001)

933MHz (October 2001)

Mobile Intel® Celeron® Processor

Same

MMX (57 new instructions) /

Streaming SIMD Extensions (70 new instructions)

Same

256KB / full speed (Advanced Transfer Cache)

256-bit data path / quad-wide cache line / ECC

Intelligent buffering of read and stores (called

Advanced System Buffering with 4 writeback buffers,

6 fill buffers, 8 bus queue entries) / Data Prefetch Logic

8-way set associative

Integrated / unified (internal die; on die)

Write-through or write-back (programmable per line),

uncacheable, write-protect

Non-blocking / pipelined burst synchronous

Same

100MHz or 133MHz frontside bus

Same

0.13u

1.1 volts for Ultra Low Voltage processors

1.15 volts for Low Voltage processors

1.4 or 1.45 volts for others

Micro-Flip Chip Ball Grid Array (Micro-FCBGA)

Micro-Flip Chip Pin Grid Array (Micro-FCPGA)

650/100MHz Ultra Low Voltage (January 2002)

650/100MHz Low Voltage (October 2001)

700MHz/100MHz Ultra Low Voltage (September 2002)

733MHz/133MHz Low Voltage (April 2002)

733MHz/133MHz Ultra Low Voltage (September 2002)

800MHz/133MHz Ultra Low Voltage (January 2003)

866MHz/133MHz Low Voltage (January 2003)

1GHz/133MHz (April 2002)

1.06GHz/133MHz (January 2002)

1.13GHz/133MHz (January 2002)

1.2GHz/133MHz (January 2002)

1.33GHz/133MHz (June 2002)

The "A" is added to the "800A" in Micro-FCBGA and

Micro-FCPGA to distinguish it from the Mobile Intel

Celeron Processor 800MHz in Micro-BGA2 and

Micro-PGA2 packages

Created by IBM PC Institute

Personal Systems Reference (PSREF)