IBM 272 manual PC Processors Mobile Celeron Fall

PC Processors (Mobile Celeron) - Fall 2001

Created by IBM PC Institute Personal Systems Reference (PSREF)

Mobile Intel→ Celeron→ Processor

Vendor	Intel→	Same
Positioning	Value mobile PC	Same
Instruction architecture	IA-32 / P6 microarchitecture / CISC/RISC/micro-ops	Same
MMX™ / Streaming SIMD MMX (57 new instructions) /		MMX (57 new instructions) /
	Streaming SIMD Extensions (70 new instructions)	Streaming SIMD Extensions (70 new instructions)
L1 cache - size	16KB data; 16KB instruction	Same
L1 cache - write policy	Write-back or thru (data); write-thru (instruction)	Same
L1 cache - organization	4-way set associative	Same
L1 cache - bus	64-bit / full speed / non-blocking	Same
L1 cache - parity	Parity in cache and internal registers	Same
L2 cache - size	128KB / full speed	256KB / full speed (Advanced Transfer Cache)
L2 cache - data path	64-bit data path / ECC	256-bit data path / quad-wide cache line / ECC
L2 cache - buffering		Intelligent buffering of read and stores (called
		Advanced System Buffering with 4 writeback buffers,
		6 fill buffers, 8 bus queue entries) / Data Prefetch Logic
L2 cache - organization	8-way set associative / non-blocking	8-way set associative
L2 cache - controller	Integrated / unified (internal die; on die)	Integrated / unified (internal die; on die)
L2 cache - write policy	Write-through or write-back (programmable per line),	Write-through or write-back (programmable per line),
	uncacheable, write-protect	uncacheable, write-protect
L2 cache - type		Non-blocking / pipelined burst synchronous
System bus - parity	ECC on system bus; parity on address bus (frontside)	Same
System bus - speed	133MHz frontside bus	100MHz or 133MHz frontside bus
System bus - features	Nonblocking cache hierarchy	Same
Bus architecture	Independent backside and frontside buses operate	Same
	concurrently / Dual Independent Bus Architecture	Same
Execution units	2 integer/MMX units; 1 floating pt unit;1 load unit; 1 store unit	Same
Pipeline stages	Decoupled, 14 stage superpipelined	Same
Supscal dispatch/execute 5 micro-ops per cycle (3 micro-ops is typical)		Same
Superscalar issue	6 micro-ops per cycle (3 micro-ops is typical)	Same
Superscalar retire	3 micro-ops per cycle	Same
Out-of-order instructions	Yes (called dynamic execution)	Same
Branch prediction	Dynamic (based on history) / 512 entry BTB	Same
Speculative execution	Yes	Same
Math coprocessor	Pipelined math coprocessor	Same
Internal processing	32-bits (300 bit internal bus width) / 32-bit word size	Same
External data bus	64-bit system bus with ECC	Same
External address bus	36-bits (64GB physical address space; 64TB virtual)	Same
User registers	8 GPR, 8 FP, 40 more GPR via register renaming	Same
Cache line size	32 bytes (8 bytes x 4 chunks)	Same
Power management	Quick Start and Deep Sleep	Same
Multiple processors	No SMP support	Same
Technology (micron)	0.18u	0.13u
CPU voltage	1.7 volts	1.1 volts for Ultra Low Voltage processors
		1.15 volts for Low Voltage processors
		1.4 or 1.45 volts for others
Package type	Micro-Flip Chip Ball Grid Array (Micro-FCBGA)	Micro-Flip Chip Ball Grid Array (Micro-FCBGA)
	Micro-Flip Chip Pin Grid Array (Micro-FCPGA)	Micro-Flip Chip Pin Grid Array (Micro-FCPGA)
Frequency (available)	733MHz (October 2001)	650/100MHz Ultra Low Voltage (January 2002)
	800A MHz (October 2001)	650/100MHz Low Voltage (October 2001)
	866MHz (October 2001)	700MHz/100MHz Ultra Low Voltage (September 2002)
	933MHz (October 2001)	733MHz/133MHz Low Voltage (April 2002)
	The "A" is added to the "800A" in Micro-FCBGA and	733MHz/133MHz Ultra Low Voltage (September 2002)
		800MHz/133MHz Ultra Low Voltage (January 2003)
	Micro-FCPGA to distinguish it from the Mobile Intel
		866MHz/133MHz Low Voltage (January 2003)
	Celeron Processor 800MHz in Micro-BGA2 and
		1GHz/133MHz (April 2002)
	Micro-PGA2 packages
		1.06GHz/133MHz (January 2002)
		1.13GHz/133MHz (January 2002)
		1.2GHz/133MHz (January 2002)
		1.33GHz/133MHz (June 2002)

All trademarks are the property of their respective owners	(20INTEL) Compiled by Roger Dodson, IBM. January 2003
♥ IBM Corp.