PC Processors (Pentium 4 - Prescott)Code name
Micro-architecture
MMX™ / Streaming SIMD
SSE2
SSE3
Hyper-Threading
L1 cache - bus
L1 data cache
L1 instruction cache
L2 cache - size
L2 cache - data path
L3 cache
System bus
Memory addressability
System bus - width
Execution units
Out-of-order instructions
Branch prediction
Speculative execution
Math coprocessor
Compatibility
Cache line size
Multiple processors
Other features
Technology
Package and connector
Frequency
and available date
Chipset support
All trademarks are the property of their respective owners
© IBM Corp.
(34INTEL) Compiled by Roger Dodson, IBM. February 2004
Prescott
IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology)
MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
Streaming SIMD Extensions 2 (144 new instructions)
Streaming SIMD Extensions 3 (13 new instructions)
800MHz system bus processors:
Hyper-Threading (HT) Technology (hardware support for multi-threaded applications)
256-bit data path / full speed
16KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated
Size not published / holds 12,000 micro-ops / 8-way set associative / integrated /
called Execution Trace Cache; caches decoded x86 instructions (micro-ops)
1MB / full speed (Advanced Transfer Cache)
256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte
sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC
None
533 or 800MHz (transfers data four times per clock) / address bus transfers at two times per clock /
64 byte cache line size
64GB memory addressability / 36-bit addressing / address bus is double clocked at 200, 266, or 400MHz
64-bit data path
2 integer units; 1 floating point units; 1 load unit; 1 store unit
Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine)
Yes
Dynamic (based on history) / 4KB Branch Target Buffer
Yes (Advanced Dynamic Execution)
Pipelined floating point unit / handles 128-bit floating point registers
Compatible with IA-32 software
128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data
No SMP support
Thermal monitoring, built-in self test, IEEE 1149.1 standard test access port and boundary scan
90nm (nanometer) or 0.09u (micron)
Flip-Chip Pin Grid Array (FC-mPGA4) requires 478-pin surface mount Zero Insertion Force (ZIF) socket
named mPGA478B socket
2.80A GHz with 533MHz system bus available February 2004
2.80E GHz with 800MHz system bus with Hyper-Threading Technology available February 2004
3.00E GHz with 800MHz system bus with Hyper-Threading Technology available February 2004
3.20E GHz with 800MHz system bus with Hyper-Threading Technology available February 2004
3.40E GHz with 800MHz system bus with Hyper-Threading Technology available February 2004
Intel 865 family with single or dual channel DDR-SDRAM memory
Intel 875P with single or dual channel DDR-SDRAM memory
Intel
®
Pentium
®
4 for desktop systems
Created by IBM PC Institute
Personal Systems Reference (PSREF)