IBM 272 manual PC Processors Pentium III Tualatin, 133MHz, Flip-Chip Pin Grid Array-2 FC-PGA2

PC Processors (Pentium III - Tualatin)					Created by IBM PC Institute
					Personal Systems Reference (PSREF)
	Intel→ Pentium→ III for desktop and entry-level workstations and servers
	Code name	Tualatin (pronounced "TWO-ala-tin")
	Instruction architecture	IA-32 / CISC/RISC/micro-ops
	MMX™ / Streaming SIMD	MMX (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
	L1 cache - bus	64-bit / full speed
	L1 cache - size/controller	16KB data; 16KB instruction / integrated / non-blocking
	L1 cache - write policy	Write-back or thru (data); write-thru (instruction)
	L1 cache - organization	4 way set associative (data); 2 way set associative (instruction)
	L2 cache - size	256 or 512KB / full speed (Advanced Transfer Cache)
	L2 cache - data path	256-bit data path / quad-wide cache line / ECC
	L2 cache - buffering	Intelligent buffering of read and stores (called Advanced
		System Buffering with 4 writeback buffers, 6 fill buffers,
		8 bus queue entries)
	L2 cache - organization	8-way set associative
	L2 cache - controller	Integrated / unified (internal die; on die)
	L2 cache - write policy	Write-through or write-back (programmable per line), uncacheable, write-protect
	L2 cache - type	Non-blocking / pipelined burst synchronous
	Frontside bus - speed	133MHz
	Memory addressability	64GB memory addressability
	System bus - width	64-bit system bus with ECC
	System bus - parity	ECC on system bus; parity on address bus (frontside bus)
	Execution units	2 integer/MMX units; 1 floating point unit; 1 load unit; 1 store unit
	Supscal dispatch/execute 5 micro-ops per cycle (3 micro-ops is typical); Pipeline stages: decoupled, 14 stage superpipelined
	Superscalar issue	6 micro-ops per cycle (3 micro-ops is typical)
	Superscalar retire	3 micro-ops per cycle
	Out-of-order instructions	Yes (called dynamic execution)
					L2 cache bus also called Backside Bus
	Branch prediction	Dynamic (based on history) / 512 entry BTB / typically
		predicts 10 to 15 nested branches			Memory or system bus also called Frontside Bus
	Speculative execution	Yes (typically 20 to 30 instructions beyond counter
		with an average of 5 branches)
	Math coprocessor	Pipelined math coprocessor
	Processor serial number	None
	Serial number	Unique processor serial number
	Bus architecture	Independent backside and frontside buses operate concurrently / Dual Independent Bus Architecture (DIB)
	Internal processing	32-bits (300 bit internal bus width)
	User registers	8 GPR, 8 FP, 8 FPscalar and SIMD, 40 more GPR via register renaming
	Cache line size	32 bytes (8 bytes x 4 chunks); burst mode bus of addr-data-data-data
	Power management	System Management Mode (SMM)
	Multiple processors	Some support 2-way SMP with appropriate chipset support
	Technology (micron)	0.13u
	Package type	Flip-Chip Pin Grid Array-2 (FC-PGA2)
	Connector	Requires Socket 370 (PGA370)
	Frequency (MHz)	900 MHz Ultra Low Voltage (DP) 512KB L2 cache for entry-level workstations and servers (announced Jan 2003)
		933 MHz Low Voltage with 512KB L2 cache for blade servers (announced September 2002)
		1.0A GHz	256KB L2 cache	for desktop, entry-level workstations and servers (announced August 2001)
		1.0 GHz Low Voltage (DP) 512KB L2 cache for entry-level workstations and servers (announced January 2003)
		1.13A GHz	256KB L2 cache	for desktop, entry-level workstations and servers (announced August 2001)
		1.13 GHz-S 512KB L2 cache		for servers (announced June 2001)
		1.20 GHz	256KB L2 cache	for desktop, entry-level workstations and servers (announce August 2001)
		1.26 GHz-S 512KB L2 cache		for servers (announced August 2001)
		1.4 GHz-S	512KB L2 cache	for servers and blade servers (announced January 2002)
	Chipset support	Intel 815x, 820x, 840 and others
		ServerWorks→ HE-SL and others
	Server blade support	Pentium III at 933MHz and 1.4GHz supported in "Performance Server Blades"

All trademarks are the property of their respective owners	(17INTEL) Compiled by Roger Dodson, IBM. January 2003
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