PC Processors (Mobile Celeron - Northwood)Code name
Micro-architecture
MMX™ / Streaming SIMD
SSE2
Power mgmt technology
L1 cache - bus
L1 data cache
L1 instruction cache
L2 cache - size
L2 cache - data path
System bus
Memory addressability
System bus - width
Execution units
Out-of-order instructions
Branch prediction
Speculative execution
Math coprocessor
Compatibility
Cache line size
Multiple processors
Technology (micron)
Voltage
Package and connector
Frequency (MHz)
and available date
Chipset support
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© IBM Corp.
(27INTEL) Compiled by Roger Dodson, IBM. November 2003
Northwood
IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology)
MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
Streaming SIMD Extensions 2 (144 new instructions)
AutoHALT, Stop-Grant, Sleep, Deep Sleep
256-bit data path / full speed
8KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated
Size not published / holds 12,000 micro-ops / 8-way set associative / integrated /
called Execution Trace Cache; caches decoded x86 instructions (micro-ops)
256KB / full speed (Advanced Transfer Cache)
256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte
sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC
400MHz (transfers data four times per clock) / address bus transfers at two times per clock / 64 byte cache line size
64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz
64-bit data path
2 integer units; 1 floating point units; 1 load unit; 1 store unit
Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine)
Yes
Dynamic (based on history) / 4KB Branch Target Buffer
Yes (Advanced Dynamic Execution)
Pipelined floating point unit / handles 128-bit floating point registers
Compatible with IA-32 software
128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data
No SMP support
0.13u
1.3 volts
Micro Flip-Chip Pin Grid Array (uFCPGA) requires 478-pin surface mount Zero Insertion Force (ZIF) socket
1.26GHz available April 2003
1.4GHz available June 2002
1.5GHz available June 2002
1.6GHz available September 2002
1.7GHz available September 2002
1.8GHz available September 2002
2.0GHz available January 2003
2.2GHz available April 2003
2.4GHz available June 2003
2.5GHz available November 2003
Intel 845MZ with DDR-SDRAM memory
Intel 845MP with DDR-SDRAM memory
Intel 852GM, 852GME, 852PM with DDR-SDRAM memory
Other compatible chipsets
Mobile Intel
®
Celeron
®
for value mobile systems
Created by IBM PC Institute
Personal Systems Reference (PSREF)