IBM 272 PC Processors Mobile Celeron Northwood, Mobile Intel→ Celeron→ for value mobile systems

PC Processors (Mobile Celeron - Northwood)

Created by IBM PC Institute Personal Systems Reference (PSREF)

Mobile Intel→ Celeron→ for value mobile systems
Code name	Northwood
Micro-architecture	IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology)
MMX™ / Streaming SIMD	MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
SSE2	Streaming SIMD Extensions 2 (144 new instructions)
Power mgmt technology	AutoHALT, Stop-Grant, Sleep, Deep Sleep
L1 cache - bus	256-bit data path / full speed
L1 data cache	8KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated
L1 instruction cache	Size not published / holds 12,000 micro-ops / 8-way set associative / integrated /
	called Execution Trace Cache; caches decoded x86 instructions (micro-ops)
L2 cache - size	256KB / full speed (Advanced Transfer Cache)
L2 cache - data path	256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte
	sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC
System bus	400MHz (transfers data four times per clock) / address bus transfers at two times per clock / 64 byte cache line size
Memory addressability	64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz
System bus - width	64-bit data path
Execution units	2 integer units; 1 floating point units; 1 load unit; 1 store unit
	Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine)
Out-of-order instructions	Yes
Branch prediction	Dynamic (based on history) / 4KB Branch Target Buffer
Speculative execution	Yes (Advanced Dynamic Execution)
Math coprocessor	Pipelined floating point unit / handles 128-bit floating point registers
Compatibility	Compatible with IA-32 software
Cache line size	128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data
Multiple processors	No SMP support
Technology (micron)	0.13u
Voltage	1.3 volts
Package and connector	Micro Flip-Chip Pin Grid Array (uFCPGA) requires 478-pin surface mount Zero Insertion Force (ZIF) socket
Frequency (MHz)	1.26GHz available April 2003
and available date	1.4GHz available June 2002
	1.5GHz available June 2002
	1.6GHz available September 2002
	1.7GHz available September 2002
	1.8GHz available September 2002
	2.0GHz available January 2003
	2.2GHz available April 2003
	2.4GHz available June 2003
	2.5GHz available November 2003
Chipset support	Intel 845MZ with DDR-SDRAM memory
	Intel 845MP with DDR-SDRAM memory
	Intel 852GM, 852GME, 852PM with DDR-SDRAM memory
	Other compatible chipsets
All trademarks are the property of their respective owners		(27INTEL) Compiled by Roger Dodson, IBM. November 2003
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