PC Processors (Pentium 4)Code name
Micro-architecture
MMX™ / Streaming SIMD
SSE2
L1 cache - bus
L1 data cache
L1 instruction cache
L2 cache - size
L2 cache - data path
Front Side Bus
Memory addressability
Front Side Bus - width
Execution units
Out-of-order instructions
Branch prediction
Speculative execution
Math coprocessor
Compatibility
Cache line size
Multiple processors
Technology (micron)
Transistors
Package and connector
Frequency (MHz)
and available date
Chipset support
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© IBM Corp.
(14INTEL) Compiled by Roger Dodson, IBM. August 2001
Willamette
IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology)
MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
Streaming SIMD Extensions 2 (144 new instructions)
256-bit data path / full speed
8KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated
Size not published / holds 12,000 micro-ops / 8-way set associative / integrated /
called Execution Trace Cache; caches decoded x86 instructions (micro-ops)
256KB / full speed (Advanced Transfer Cache)
256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte
sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC
400MHz (transfers data four times per clock) / address bus transfers at two times per clock / 64 byte cache line size
64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz
64-bit data path
2 integer units; 1 floating point units; 1 load unit; 1 store unit
Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine)
Yes
Dynamic (based on history) / 4KB Branch Target Buffer
Yes (Advanced Dynamic Execution)
Pipelined floating point unit / handles 128-bit floating point registers
Compatible with IA-32 software
128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data
No SMP support
0.18u
~42 million with die size of 217 square millimeters
1. Pin Grid Array (PGA) requires 423-pin Zero Insertion Force (ZIF) socket named Intel Socket 423 (PGA423);
used with RDRAM-based 850 chipset
2. Flip-Chip Pin Grid Array-2 (FC-PGA2) requires 478-pin surface mount Zero Insertion Force (ZIF) socket
named mPGA478B socket; used with SDRAM-based chipset (such as 845 chipset)
1.3GHz: 423-pin available January 2001
1.4GHz: 423-pin available November 2000
1.5GHz: 423-pin available November 2000, 478-pin available August 2001
1.6GHz: 423-pin available November 2000, 478-pin available August 2001
1.7GHz: 423-pin available November 2000, 478-pin available August 2001
1.8GHz: 423-pin available November 2000, 478-pin available August 2001
1.9GHz: 423-pin available November 2000, 478-pin available August 2001
2.0GHz: 423-pin available November 2000, 478-pin available August 2001
Intel 850 with dual channel RDRAM memory
Intel 845 with SDRAM memory
Intel
®
Pentium
®
4 for high performance desktop systems
1.3GHz, 1.4GHz, 1.5GHz, 1.6GHz, 1.7GHz, 1.8GHz, 1.9GHz, 2.0GHz
Created by IBM PC Institute
Personal Systems Reference (PSREF)