IBM 272 manual PC Processors Pentium 4 Extreme Edition

PC Processors (Pentium 4 Extreme Edition)

Created by IBM PC Institute Personal Systems Reference (PSREF)

Intel→ Pentium→ 4 Extreme Edition for high-end gamers and power users

Code name	None
Formal name	Intel Pentium 4 Processor with HT Technology Extreme Edition
Micro-architecture	IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology)
MMX™ / Streaming SIMD	MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
SSE2	Streaming SIMD Extensions 2 (144 new instructions)
Hyper-Threading	Hyper-Threading (HT) Technology (hardware support for multi-threaded applications)
L1 cache - bus	256-bit data path / full speed
L1 data cache	8KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated
L1 instruction cache	Size not published / holds 12,000 micro-ops / 8-way set associative / integrated /
	called Execution Trace Cache; caches decoded x86 instructions (micro-ops)
L2 cache - size	512KB / full speed (Advanced Transfer Cache)
L2 cache - data path	256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte
	sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC
L3 cache	2MB / full speed
L3 cache - data path	256-bit data path (32 bytes) / transfers on each bus clock / 64 byte cache line size / 8-way set associative /
	write-back / parity / integrated / unified (internal die; on die)
System bus	800MHz (transfers data four times per clock) / address bus transfers at two times per clock /
	64 byte cache line size
Memory addressability	64GB memory addressability / 36-bit addressing / address bus is double clocked at 200, 266, or 400MHz
Frontside bus - width	64-bit data path
Execution units	2 integer units; 1 floating point units; 1 load unit; 1 store unit
	Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine)
Out-of-order instructions	Yes
Branch prediction	Dynamic (based on history) / 4KB Branch Target Buffer
Speculative execution	Yes (Advanced Dynamic Execution)
Math coprocessor	Pipelined floating point unit / handles 128-bit floating point registers
Compatibility	Compatible with IA-32 software
Cache line size	128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data
Multiple processors	No SMP support
Technology (micron)	0.13u
Transistors	~108 million
Package and connector	Flip-Chip Pin Grid Array-2 (FC-PGA2) requires 478-pin surface mount Zero Insertion Force (ZIF) socket
	named mPGA478B socket
Frequency	3.2GHz	available November 2003
and available date	3.4GHz	available February 2004
Chipset support	Intel 865 family
	Intel 875P

All trademarks are the property of their respective owners	(32INTEL) Compiled by Roger Dodson, IBM. February 2004
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