System Control | Port A (Hex | 0092) | |
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Bit | Function |
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Reserved |
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3 | Security | lock | latch |
2 | Reserved (must be set to 0) | ||
1 | Alternate | gate | A20 |
0 | Alternate | hot | reset |
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Figure | Control | Port | A | (Hex | 0092) |
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Bits | These | bits | are | reserved. |
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Bit | 3 | This | bit | provides | a | security | lock for the secured area of | |||||||||||||||
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| RT/CMOS. If this bit is set to 1, the |
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| password | is | locked | by | the | software. After | this | bit | is | set | |||||||||||
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| by | POST, | it | can | be | cleared | only | by | turning | the | system |
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| off. |
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Bit | 2 | This | bit | is | reserved. |
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Bit | 1 | This | bit | is used to enable the ‘addressA20 ) | 20’ signal | ( |
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| when | the | microprocessor | is | in | the real address mode. If | |||||||||||||||
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| this bit is A20set cannotto0, be used in real mode |
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| addressing. This | bit | is | set |
| to 0 during a system reset. |
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Bit | 0 | This | bit | provides an alternative method of resetting the |
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| system microprocessor. This alternative method |
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| supports | operating systems requiring faster operation |
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| than that provided on the IBM Personal Computer AT. |
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| Resetting the system microprocessor switches the |
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| microprocessor from protected mode to real address |
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| mode. |
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| This | bit | is set to 0 by either a system reset or a write | ||||||||||||||||||
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| operation. If | a | write | operation | changes | this bit from 0 | to | ||||||||||||||
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| 1, | the | ‘processor | reset’ | signal | is | pulsed | after | the | reset | |||||||||||
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| has occurred. While the reset is occurring, the latch |
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| remains | set | so | that | POST | can |
| read | this | bit. If | the | bit | is | ||||||||
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| set | to |
| 0, POST | assumes | that | the | system | was | just |
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| powered | on. If the bit is | set to 1, POST assumes that |
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| the | microprocessor | has | been |
| switched | from | protected |
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| mode | to | real | mode. |
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| If | bit | 0 is used to reset | the system microprocessor to the | |||||||||||||||||
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| real | mode, | use | the | following | procedure: |
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1. Disable all maskable and nonmaskable interrupts.