2. Reset the system microprocessor by writing a 1 to bit 0.
3.Issue a Halt instruction to the system microprocessor.
4.Reenable all maskable and nonmaskable interrupts.
If you do not follow this procedure, the results are unpredictable.
Note: Whenever possible, use BIOS as an interface to reset the system microprocessor to the real mode. For more information about resetting the system microprocessor, referIBM toPersonalthe
System/2 and Personal Computer BIOS
Interface.
System | Control Port | B | (Hex | 0061) |
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Bit | definitions | for | the | write | and | read functions of this port are shown | |||||
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| Reserved |
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| 3 | Enable | channel | check |
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| 2 | Enable | PCI | SERR# |
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| 1 | Enable | speaker | data |
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| 0 |
| Timer 2 gate to speaker |
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Figure | Control | Port | B | (Hex | 0061, Write) | ||||||
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| 7 |
| PCI SERR# (PCI error) status |
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| 6 |
| Channel | check status |
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| 5 |
| Timer | 2 output |
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| 4 | Toggles with each refresh request |
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| 3 | Enable | channel | check |
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| 2 | Enable PCI SERR# (PCI error) check |
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| 1 | Enable | speaker | data |
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| 0 |
| Timer | 2 gate | to | speaker |
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Figure | Port B | (Hex 0061, | Read) | |||
Bit 7 | If a system | board | error | occurs | and the PCI SERR# line is | |
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| System | Board |
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