Specifications
Figure
Performance Specifications
Device/Cycle |
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| (66 | MHz) |
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Microprocessor |
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| 200 | or | 233 |
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L1 cache | (64bit) |
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read/write hit |
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| 1 | CPUCLK |
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L2 cache (64bit) (for | not all |
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models) |
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| 90 | ns | (60 | ns) |
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read hit |
| 90 | ns | (60 | ns) |
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write hit |
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Memory | (64bit) | (see | Note) |
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read, | page | hit |
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| 240 | ns |
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read, | raw | miss |
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| 285 | ns |
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read, | page | miss |
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| 345 | ns |
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posted write |
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| 90 | ns |
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write | retire | rate | from | 135 | ns |
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write buffer |
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Note: |
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The cycle times shown for | access | to | system | ||||||||
board | RAM | are based on | 70 |
| ns | EDO | memory. | ||||
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Figure |
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System Overview