
EM78M611E
Universal Serial Bus Series Microcontroller
  | Binary Instruction | 
  | Hex  | 
  | Mnemonic  | 
  | Operation  | 
  | Status Affected  | ||
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0  | 0001  | 10rr  | rrrr  | 
  | 01rr  | DECA R  | 
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  | Z  | ||
0  | 0001  | 11rr  | rrrr  | 
  | 01rr  | DEC R  | 
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  | Z  | ||
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0  | 0010  | 00rr  | rrrr  | 
  | 02rr  | OR A,R  | 
  | A ∨ VR → A  | 
  | Z  | |
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0  | 0010  | 01rr  | rrrr  | 
  | 02rr  | OR R,A  | 
  | A ∨ VR → R  | 
  | Z  | |
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0  | 0010  | 10rr  | rrrr  | 
  | 02rr  | AND A,R  | 
  | A & R → A  | 
  | Z  | |
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0  | 0010  | 11rr  | rrrr  | 
  | 02rr  | AND R,A  | 
  | A & R → R  | 
  | Z  | |
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0  | 0011  | 00rr  | rrrr  | 
  | 03rr  | XOR A,R  | 
  | A ⊕ R → A  | 
  | Z  | |
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0  | 0011  | 01rr  | rrrr  | 
  | 03rr  | XOR R,A  | 
  | A ⊕ R → R  | 
  | Z  | |
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0  | 0011  | 10rr  | rrrr  | 
  | 03rr  | ADD A,R  | 
  | A + R → A  | 
  | Z, C, DC  | |
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0  | 0011  | 11rr  | rrrr  | 
  | 03rr  | ADD R,A  | 
  | A + R → R  | 
  | Z, C, DC  | |
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0  | 0100  | 00rr  | rrrr  | 
  | 04rr  | MOV A,R  | 
  | R → A  | 
  | Z  | |
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0  | 0100  | 01rr  | rrrr  | 
  | 04rr  | MOV R,R  | 
  | R → R  | 
  | Z  | |
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0  | 0100  | 10rr  | rrrr  | 
  | 04rr  | COMA R  | 
  | /R → A  | 
  | Z  | |
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0  | 0100  | 11rr  | rrrr  | 
  | 04rr  | COM R  | 
  | /R → R  | 
  | Z  | |
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0  | 0101  | 00rr  | rrrr  | 
  | 05rr  | INCA R  | 
  | R+1 → A  | 
  | Z  | |
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0  | 0101  | 01rr  | rrrr  | 
  | 05rr  | INC R  | 
  | R+1 → R  | 
  | Z  | |
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0  | 0101  | 10rr  | rrrr  | 
  | 05rr  | DJZA R  | 
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  | None  | ||
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0  | 0101  | 11rr  | rrrr  | 
  | 05rr  | DJZ R  | 
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  | None  | ||
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0  | 0110  | 00rr  | rrrr  | 
  | 06rr  | RRCA R | 
  | R(n) →   | 
  | C  | |
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  | R(0) → C, C → A(7)  | 
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0  | 0110  | 01rr  | rrrr  | 
  | 06rr  | RRC R  | 
  | R(n) →   | 
  | C  | |
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  | R(0) → C, C → R(7)  | 
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0  | 0110  | 10rr  | rrrr  | 
  | 06rr  | RLCA R | 
  | R(n) → A(n+1),  | 
  | C  | |
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  | R(7) → C, C → A(0)  | 
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0  | 0110  | 11rr  | rrrr  | 
  | 06rr  | RLC R  | 
  | R(n) → R(n+1),  | 
  | C  | |
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  | R(7) → C, C → R(0)  | 
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0  | 0111  | 00rr  | rrrr  | 
  | 07rr  | SWAPA R  | 
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  | None  | ||
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0  | 0111  | 01rr  | rrrr  | 
  | 07rr  | SWAP R  | 
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  | None  | ||
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0  | 0111  | 10rr  | rrrr  | 
  | 07rr  | JZA R  | 
  | R+1 → A, skip if zero  | 
  | None  | |
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0  | 0111  | 11rr  | rrrr  | 
  | 07rr  | JZ R | 
  | R+1 → R, skip if zero  | 
  | None  | |
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0  | 100b  | bbrr  | rrrr  | 
  | 0xxx  | BC R,b  | 
  | 0 → R(b)  | 
  | None2  | |
0  | 101b  | bbrr  | rrrr  | 
  | 0xxx  | BS R,b  | 
  | 1 → R(b)  | 
  | None  | |
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0  | 110b  | bbrr  | rrrr  | 
  | 0xxx  | JBC R,b  | 
  | if R(b)=0, skip  | 
  | None  | |
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0  | 111b  | bbrr  | rrrr  | 
  | 0xxx  | JBS R,b  | 
  | if R(b)=1, skip  | 
  | None  | |
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1  | 00kk kkkk kkkk  | 
  | 1kkk  | CALL k  | 
  | PC+1 → [SP],  | 
  | None  | |||
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  | (Page, k) → PC  | 
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1  | 01kk kkkk kkkk  | 
  | 1kkk  | JMP k  | 
  | (Page, k) → PC  | 
  | None  | |||
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1  | 1000  | kkkk kkkk  | 
  | 18kk  | MOV A,k  | 
  | k → A  | 
  | None  | ||
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1  | 1001  | kkkk kkkk  | 
  | 19kk  | OR A,k  | 
  | A ∨ k → A  | 
  | Z  | ||
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1  | 1010  | kkkk kkkk  | 
  | 1Akk  | AND A,k  | 
  | A & k → A  | 
  | Z  | ||
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1  | 1011  | kkkk kkkk  | 
  | 1Bkk  | XOR A,k  | 
  | A ⊕ k → A  | 
  | Z  | ||
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1  | 1100  | kkkk kkkk  | 
  | 1Ckk  | RETL k  | 
  | k → A, [Top of Stack] → PC  | 
  | None  | ||
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1  | 1101  | kkkk kkkk  | 
  | 1Dkk  | SUB A,k  | 
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  | Z, C, DC  | |||
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1  | 1111  | kkkk kkkk  | 
  | 1Fkk  | ADD A,k  | 
  | k+A → A  | 
  | Z, C, DC  | ||
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Note: 1 This instruction is applicable to IOCx only.
2This instruction is not recommended for RE, RF operation.
38 •  | Product Specification (V1.1) 11.22.2006 | 
(This specification is subject to change without further notice)