Intel manual Intel, Manual, IXD1110 CPU Logic Probe Connectors, IXD1110 Demo Board

Development Kit

Document Number: 250807

Revision Number: 003

Revision Date: June 27, 2003

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Figure 16. Intel

Manual

D

C

2,10 uPx_Add[10:0]

2,9 uPx_RdN

2,9 uPx_WrN

2,9 uPx_CsN

2,9 uPx_RdyN

9,10 Bus_Busy

9,10 Bus_Request

9,10 Bus_Grant

9,10 CsN

9,10 GenP_CsN

9,10 RD/~WR

9,10 Start_XFER

9,10 TA

9,10 BUS_CLK

2,9,10 uPx_Data[31:0]

uPx_Add0

uPx_Add1

uPx_Add2

uPx_Add3

uPx_Add4

uPx_Add5

uPx_Add6

uPx_Add7

uPx_Add8

uPx_Add9

uPx_Add10

uPx_RdN

uPx_WrN

uPx_CsN

uPx_RdyN

Bus_Busy

Bus_Request

Bus_Grant

CsN

GenP_CsN

RD/~WR

Start_XFER

TA

BUS_CLK

uPx_Data0

uPx_Data1

uPx_Data2

uPx_Data3

uPx_Data4

uPx_Data5

uPx_Data6

uPx_Data7

uPx_Data8

uPx_Data9

uPx_Data10

uPx_Data11

uPx_Data12

uPx_Data13

uPx_Data14

uPx_Data15

uPx_Data16

uPx_Data17

uPx_Data18

uPx_Data19

uPx_Data20

uPx_Data21

uPx_Data22

uPx_Data23

uPx_Data24

uPx_Data25

uPx_Data26

uPx_Data28

uPx_Data27

uPx_Data29

uPx_Data30

uPx_Data31

2,10	HRESET	HRESET
		POR
2,10	POR
2,10	IRQ	IRQ
2,9	TxPauseFR	TxPauseFR
		TxPauseAdd0
2,9	TxPauseAdd0
		TxPauseAdd1
2,9	TxPauseAdd1
		TxPauseAdd2
2,9	TxPauseAdd2
		TxPauseAdd3
2,9	TxPauseAdd3

D

C

® IXD1110 CPU Logic Probe Connectors

B

A

PROBE C: Address

PROBE A: Data Bus Bus & IXF1110

Signals

GND

GND

U19A

P6434 Probe

U20C

P6434 Probe

1

GND

GND

38

1

GND

GND

38

2

GND

GND

37

2

GND

GND

37

BUS_CLK

3

CLK_0 CLK_1

36

3

CLK_3

Q1

36

IRQ

uPx_Data31

4

A3_7

A1_7

35

uPx_Data15

4

C3_7

C1_7

35

uPx_Data30

5

A3_6

A1_6

34

uPx_Data14

5

C3_6

C1_6

34

uPx_RdN

uPx_Data29

6

A3_5

A1_5

33

uPx_Data13

6

C3_5

C1_5

33

uPx_WrN

uPx_Data28

7

A3_4

A1_4

32

uPx_Data12

7

C3_4

C1_4

32

uPx_CsN

uPx_Data27

8

A3_3

A1_3

31

uPx_Data11

8

C3_3

C1_3

31

uPx_Data26

9

A3_2

A1_2

30

uPx_Data10

uPx_Add10

9

C3_2

C1_2

30

uPx_RdyN

uPx_Data25

10

A3_1

A1_1

29

uPx_Data9

uPx_Add9

10

C3_1

C1_1

29

uPx_Data24

11

A3_0

A1_0

28

uPx_Data8

uPx_Add8

11

C3_0

C1_0

28

Bus_Grant

uPx_Data23

12

A2_7

A0_7

27

uPx_Data7

uPx_Add7

12

C2_7

C0_7

27

Bus_Busy

uPx_Data22

13

A2_6

A0_6

26

uPx_Data6

uPx_Add6

13

C2_6

C0_6

26

Bus_Request

uPx_Data21

14

A2_5

A0_5

25

uPx_Data5

uPx_Add5

14

C2_5

C0_5

25

CsN

uPx_Data20

15

A2_4

A0_4

24

uPx_Data4

uPx_Add4

15

C2_4

C0_4

24

uPx_Data19

16

A2_3

A0_3

23

uPx_Data3

uPx_Add3

16

C2_3

C0_3

23

GenP_CsN

uPx_Data18

17

A2_2

A0_2

22

uPx_Data2

uPx_Add2

17

C2_2

C0_2

22

RD/~WR

uPx_Data17

18

A2_1

A0_1

21

uPx_Data1

uPx_Add1

18

C2_1

C0_1

21

Start_XFER

uPx_Data16

19

A2_0

A0_0

20

uPx_Data0

uPx_Add0

19

C2_0

C0_0

20

TA

GND GND GND GND GND

GND GND GND GND GND

39

40

41

42

43

39

40

41

42

43

GND

GND

PROBE D:

IXF1110 Pause

I/F Signals

				GND
		U21D		P6434 Probe
	1	GND				GND	38
	2	GND				GND	37
	3	Q0				CLK_2	36
TxPauseFR								HRESET
	4	D3_7				D1_7	35
TxPauseAdd0	5	D3_6				D1_6	34	POR
TxPauseAdd1	6	D3_5				D1_5	33
TxPauseAdd2	7	D3_4				D1_4	32
TxPauseAdd3	8	D3_3				D1_3	31
	9	D3_2				D1_2	30
	10	D3_1				D1_1	29
	11	D3_0				D1_0	28
	12	D2_7				D0_7	27
	13	D2_6				D0_6	26
	14	D2_5				D0_5	25
	15	D2_4				D0_4	24
	16	D2_3				D0_3	23
	17	D2_2				D0_2	22
	18	D2_1				D0_1	21
	19	D2_0				D0_0	20
		GND GND GND GND GND
		39	40	41	42	43

GND

X = DO NOT INSTALL

B

Intel Communications Group					A
9750 Goethe Road
Sacramento, CA 95827
Title
	IXD1110 - FX DEMO Board
Size	Document Number			Rev
B	CPU I/F Logic Probe Connectors			A1
Date:	Friday, May 24, 2002	Sheet 11 of	14

IXD1110 Demo Board

37

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