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Intel IXD1110 Optional Configurations, Reset Jumper JP2, JTAG Test Signals, Standard Operation

Models: IXD1110

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IXD1110 Demo Board

6.0Optional Configurations

6.1Reset Jumper JP2

6.1.1Standard Operation

The Reset Jumper JP2 is required for standard operation of the IXD1110 demo board. Use the HRESET position for standard operation.

The POR position is not recommended for standard operation of the IXD1110 demo board. This configuration only affects the CPU operation, and does not affect IXF1110 operation. The only difference between HRESET and POR is that POR also resets the CPU PLLs and state machines. This difference is seen when reset is asserted by pressing switch S1. For more information on the POR position of JP2, refer to Table 12 (MPC860 Reset Responses) of the Motorola* MPC860 CPU Datasheet.

6.2JTAG Test Signals

The boundary scan test port for the IXF1110 is accessed using JP1 for board-level testing. Table 3 describes JTAG test signals.

Note: For normal IXD1110 demo board operation, connect TRST_N pin 8 on JP1 to ground by jumpering pins 6 and 8 of JP1.

Table 3. JTAG Test Signals (JP1)

	Jumper	Pin	Symbol	IXF1110 Ball	Description
	Jumper	Number	Symbol	Designator	Description
		Number		Designator

		1	TDI	AC18	Test Data Input

		3	TDO	Y24	Test Data Output

	JP1	5	TMS	T16	Test Mode Select

		7	TCLK	AA29	Test Clock
		7	TCLK	AA29	Test Clock

		8	TRST	N18	Test Reset (jumper pins 6 and 8)

		2,4,6	GND	–	Connect to system ground

18	Development Kit Manual

Document Number: 250807

Revision Number: 003

Revision Date: June 27, 2003

Image 18

Intel Optional Configurations, Reset Jumper JP2, Standard Operation, JTAG Test Signals JP1, IXD1110 Demo Board

Contents

June Development Kit ManualIntel IXD1110 Demo Board Document Number Revision Number Revision Date June 27Development Kit Manual Document Number Revision Number Revision Date June 27Contents ContentsTables Intel IXD1110 Demo Board Power Revision A1Figures Intel IXD1110 Demo Board Bill of Materials Rev. A1Revision History ContentsDevelopment Kit Manual Contents Development Kit ManualDocument Number Revision Number Revision Date June 27 1.2 Additional Equipment Required 1.0 Introduction1.1 About This Kit IXD1110 Demo Board1.3.1 Features 1.3 About The IXD1110 Demo BoardIXD1110 Demo Board Table 1. Intel IXD1110 Demo Board Principal Components 1.3.2 Component Location and DescriptionFigure 1. Intel IXD1110 Demo Board Top View IntelDevelopment Kit Manual Table 1. Intel IXD1110 Demo Board Principal Components ContinuedIXD1110 Demo Board to Section 4.1, “CPU FPGA” on page 14 for more informationIXD1110 Demo Board 2.1 Setup2.0 Quick Start Development Kit Manual3.0 Typical Test Setup Figure 2. Typical Test SetupIXD1110 Demo Board Table 2. Pinout for DB-9-to-RJ-45 Connector 4.0 CPU Daughter CardFigure 3. Intel IXF1110 CPU Daughter Card IXD1110 Demo Board4.1 CPU FPGA 4.2 IXF1110 Register Modifications on StartupIXD1110 Demo Board IXD1110 Demo Board 5.0 IXF1110 Software5.1 PC Requirements Development Kit Manual5.2 Installing the IXF1110 Software 5.3 Changing the IP Address of the CPU Daughter Card OptionalIXD1110 Demo Board IXD1110 Demo Board Parity None Stops bits Flow Control NoneDevelopment Kit Manual 6.2 JTAG Test Signals 6.0 Optional Configurations6.1 Reset Jumper JP2 Table 3. JTAG Test Signals JP1IXD1110 Demo Board 7.0 LEDsTable 4. IXF1110 LED Behavior Development Kit Manual8.0 Test Points 8.1 Reset Test PointsTable 5. Intel IXF1110 Reset Test Points 8.2 IXF1110 Input Clock Test PointsTable 7. GBIC Test Points Sheet 2 of 8.4 Mictor ConnectorsTable 8. Mictor Connector Test Points Sheet 1 of IXD1110 Demo BoardTable 9. Power Test Points Sheet 1 of 8.5 Power and Ground Test PointsTable 8. Mictor Connector Test Points Sheet 2 of IXD1110 Demo BoardIXD1110 Demo Board Table 9. Power Test Points Sheet 2 ofTable 10. Ground Test Points Development Kit ManualIXD1110 Demo Board 8.6 Unused Test PointsTable 11. Unused Test Points Development Kit ManualFigure 4. Intel SchematicsIXD1110 Demo Board Power Revision A1 Power GBIC & Board ICsBoard Digital PowerIXD1110 Demo IXF1110 - Power CapsAnalog Power Figure 6. Intel IXD1110 Analog PowerX = DO NOT INSTALL SerdesPowerReset ControlX = DO NOT INSTALL BoardIXD1110 Demo Board Figure 8. Intel IXD1110 SerDes GBIC PortsX = DO NOT INSTALL Revision Date June 27IXD1110 Demo SerDes GBIC PortsX = DO NOT INSTALL BoardIXD1110 Demo Board Figure 10. Intel IXD1110 SerDes GBIC PortsX = DO NOT INSTALL Revision Date June 27IXD1110 Figure 11. IntelBoard X = DO NOT INSTALLX = DO NOT INSTALL Figure 12. IntelIXD1110 SPI4-2 SPI-4 Phase 2 - RXIXD1110 Demo LEDsX = DO NOT INSTALL BoardIXD1110 X = DO NOT INSTALLDatePower ControlIXD1110 Demo ConnectorsX = DO NOT INSTALL Date BoardIXD1110 CPU Logic Probe Connectors Figure 16. IntelManual PROBE C Address PROBE A Data Bus Bus & IXF1110 SignalsIXD1110 Demo Board 10.0 Bill of MaterialsTable 12. Intel IXD1110 Demo Board Bill of Materials Rev. A1 Development Kit ManualIXD1110 Demo Board Development Kit ManualIXD1110 Demo Board Development Kit Manual