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Motorola 700/800-Series, Embedded Controller, MVME162LX , Requirements, Features,

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Board Level Hardware Description

1

Requirements

These boards are designed to conform to the requirements of the

following documents:

❏

VME64 Specification, VITA

❏

EIA-232-D Serial Interface Specification, EIA

❏

SCSI Specification, ANSI

❏

IndustryPack Specification, VITA

Features

The following table summarizes the features of the 700/800-series

MVME162LX VMEmodule.

NCR 53C710 SCSI I/O Processor Data Manua

l

,

order number

NCR53C710DM

NCR Corporation

Microelectronics Products Division

1635 Aeroplaza Dr.

Colorado Springs, CO 80916

NCR 53C710 SCSI I/O Processor ProgrammerÕs

Guide

, order number

NCR53C710PG

SGS-THOMSON 64K (8K x 8) Timekeeper¨

SRAM Data Sheet

, order number M48T08/18

SGS-THOMSON Microelectronics

Group

Marketing Headquarters

1000 East Bell Rd.

Phoenix, AZ 85022-2699

IndustryPack Logic Interface SpeciÞcation

,

Revision 1.0, order number ANSI/VITA 4-1995

VITA (VMEbus International

Trade Association)

7825 E. Gelding Dr., Ste. 104

Scottsdale, AZ 85260-3415

Z85230 Serial Communications Controller Data

Sheet

Zilog Inc.

210 Hacienda Ave.

Campbell, CA 95008-6609

Document Title Source

Contents

Main Notice Restricted Rights Legend Preface Safety Summary Safety Depends On You Page Page Contents Page Page Page 1Board Level Hardware Description Overview Introduction Page Related Documentation Documents for the MVME162LX Other Applicable Motorola Publications Applicable Non-Motorola Publications , order number 296853 order number Requirements Features Page Page Specications Cooling Requirements Special Considerations for Elevated-Temperature Operation Page FCC Compliance Manual Terminology Page Block Diagram Functional Description Front Panel Switches and Indicators Functional Description Figure 1-1. MVME162LX Block Diagram 1-15 Data Bus Structure Microprocessor No-VMEbus-Interface Option Memory Options Page Page Page Battery Backed Up RAM and Clock VMEbus Interface and VMEchip2 I/O Interfaces Page Page Local Resources Page Local Bus Arbiter Connectors Memory Maps Local Bus Memory Map Memory Maps 1-29 1-30 Board Level Hardware Description The next table describes the Local I/O Devices portion of the local bus main memory map. Notes Table 1-4. Local Bus Memory Map (Continued) Page Table 1-5. Local I/O Devices Memory Map (Continued) Notes Table 1-5. Local I/O Devices Memory Map (Continued) VMEbus Memory Map 2Hardware Preparation and Installation Introduction Unpacking Instructions Hardware Preparation 2-2 2 System Controller Select Header (J1) Figure 2-1. MVME162LX Board Layout P1 11856.00 9708 2-4 PRIMARY SIDE IP Bus Clock Header (J11) 2SCSI Terminator Enable Header (J12) SRAM Backup Power Source Select Header (J14) Flash Write Protect Header (J16) 2IP Bus Strobe Select Header (J18) IP DMA Snoop Control Header (J19) EPROM/Flash Conguration Header (J20) 2-10 Table 2-3. EPROM/Flash Mapping 256K x 8 EPROMs Table 2-4. EPROM/Flash Mapping 512K x 8 EPROMs Table 2-5. EPROM/Flash Mapping 1M x 8 EPROMs General-Purpose Readable Jumpers Header (J21) Memory Mezzanine Options 2 Installation Instructions IP Installation on the MVME162LX 2MVME162LX Installation Page 2System Considerations Page 2-20 2 adapt a DB-25 DTE device to the RJ-45 connectors. Figure 2-3. DB-25 DCE-to-RJ-45 Adapter Installation Instructions 2-21 Figure 2-4. Typical RJ-45 Serial Cable Page 3Debugger General Information Overview of M68000 Firmware Description of 162Bug Page 162Bug Implementation Installation and Startup Page Page Page Prom Versions Autoboot Page ROMboot Network Boot Restarting the System Reset Abort Break SYSFAIL* Assertion/Negation MPU Clock Speed Calculation Memory Requirements Page Disk I/O Support Blocks Versus Sectors Device Probe Function Disk I/O via 162Bug Commands Disk I/O via 162Bug System Calls Page Default 162Bug Controller and Device Parameters Disk I/O Error Codes Network I/O Support Intel 82596 LAN Coprocessor Ethernet Driver UDP/IP Protocol Modules RARP/ARP Protocol Modules BOOTP Protocol Module TFTP Protocol Module Network Boot Control Module Network I/O Error Codes Multiprocessor Support Multiprocessor Control Register (MPCR) Method Page GCSR Method Diagnostic Facilities Manufacturing Test Process Page 4Using the 162Bug Debugger In This Chapter Entering Debugger Command Lines Terminal Input/Output Control Page Debugger Command Syntax Syntactic Variables Page Page 4-6 Page 4-8 The above program was loaded at address $0001327C. The disassembled code is shown next: Port Numbers Entering and Debugging Programs Creating a Program with the Assembler/Disassembler Downloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs Preserving the Debugger Operating Environment 162Bug Vector Table and Workspace Hardware Functions Exception Vectors Used by 162Bug 4-14 172-Bug> Page Page Page Floating Point Support Single Precision Real Double Precision Real Scientic Notation The 162Bug Debugger Command Set The 162Bug Debugger Command Set 4-21 Table 4-3. Debugger Commands 4-22 The 162Bug Debugger Command Set 4-23 4-24 A ACongure and Environment Commands Congure Board Information Block Page Set Environment to Bug/Operating System Page Page Page Page Page Page Page Page Page Page Conguring the IndustryPacks Page Page Set Environment to Bug/Operating System A-17 ENV warning example: Page B BDisk/Tape Controller Data Disk/Tape Controller Modules Supported BDisk/Tape Controller Default Congurations Note SCSI Common Command Set (CCS) devices are the only ones tested by Motorola Computer Group. e B-4 Disk/Tape Controller Data BIOT Command Parameters for Supported Floppy Types IOT Command Parameters for Supported Floppy Types B-5 e Page C CNetwork Controller Data Network Controller Modules Supported Page D D-1 DTroubleshooting CPU Boards Solving Startup Problems D-2 Caution Solving Startup Problems D-3 D-4 Troubleshooting CPU Boards TROUBLESHOOTING PROCEDURE COMPLETE. Index Numerics A B C D E F G H I J L M N O P R S T U V VMEchip2 3-24 W