Motorola MVME166IG/D2, MVME166D2 2. Local Bus Memory Map, Software, Devices Accessed, Port Size

Memory Maps

Table 1-2. Local Bus Memory Map

				Software
Address Range	Devices Accessed	Port Size	Size	Cache	Notes
				Inhibit
$00000000 - DRAMSIZE	User Programmable	D32	DRAMSIZE	N	1, 2
	(Onboard DRAM)
DRAMSIZE - $FF7FFFFF	User Programmable	D32/D16	3GB	?	3, 4
	(VMEbus or VSB)
$FF800000 - $FF8FFFFF	FLASH	D32	1MB	N	1
$FFC00000 - $FFDFFFFF	reserved	--	2MB	--	5
$FFE00000 - $FFE1FFFF	SRAM	D32	128KB	N	--
$FFE20000 - $FFEFFFFF	SRAM (repeated)	D32	896KB	N	--
$FFF00000 - $FFFEFFFF	Local I/O Devices	D32-D8	1MB	Y	3
	(Refer to next table)
$FFFF0000 - $FFFFFFFF	User Programmable	D32/D16	64KB	?	2, 4
	(VMEbus A16)

NOTES:

1.There is 1MB of FLASH in this 4MB map area. Download EPROM on the MVME166 appears at $00000000 - ROMSIZE following a local bus reset. The Download EPROM appears at 0 until the DR0 bit is cleared in the PCCchip2. The DR0 bit is located at address $FFF42000 bit 15. The EPROM must be disabled at 0 before the DRAM is enabled. The VMEchip2, VSBchip2, and DRAM map decoders are disabled by a local bus reset.

2.This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2. The local-to-VSB decoders are programmed in the VSBchip2.

3.Size is approximate.

4.Cache inhibit depends on devices in area mapped.

5.This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal.

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MVME166IG/D2 1-19