NEC 78K/0 Series ADDC

56

CHAPTER 5 EXPLANATION OF INSTRUCTIONS

User's Manual U12326EJ4V0UM

Add with Carry

ADDC Addition of Byte Data with Carry

[Instruction format] ADDC dst, src

[Operation] dst, CY ← dst + src + CY

[Operand]

Mnemonic Operand(dst,src) Mnemonic Operand(dst,src)

ADDC A, #byte ADDC A, !addr16

saddr, #byte A, [HL]

A, r Note A, [HL+byte]

r, A A, [HL+B]

A, saddr A, [HL+C]

Note Except r = A

[Flag]

ZACCY

×××

[Description]

• The destination operand (dst) specified by the 1st operand, the source operand (src) specified by the 2nd

operand and the CY flag are added and the result is stored in the destination operand (dst) and the CY flag.

The CY flag is added to the least significant bit. This instruction is mainly used to add two or more bytes.

• If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

• If the addition generates a carry out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

• If the addition generates a carry for bit 4 out of bit 3, the AC flag is set (1). In all other cases, the AC flag

is cleared (0).

[Description example]

ADDC A, [HL+B]; The A register contents and the contents at address (HL register + (B register)) and the

CY flag are added and the result is stored in the A register.

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: