NEC 78K/0 Series 3.2 Operand Address Addressing

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CHAPTER 3 ADDRESSING

User's Manual U12326EJ4V0UM

3.2 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.2.1 Implied addressing

[Function]

This addressing automatically specifies the address of the registers that function as an accumulator (A and

AX) in the general-purpose register area.

Of the 78K/0 Series instruction words, the following instructions employ implied addressing.

Instruction Register to Be Specified by Implied Addressing

MULU A register for multiplicand and AX register for product storage

DIVUW AX register for dividend and quotient storage

ADJBA/ADJBS A register for storage of numeric values targeted for decimal correction

ROR4/ROL4 A register for storage of digit data that undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format

is necessary.

[Description example]

In the case of MULU X

With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this

example, the A and AX registers are specified by implied addressing.

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: