NEC 78K/0 Series ADJBA

CHAPTER 5 EXPLANATION OF INSTRUCTIONS

83

User's Manual U12326EJ4V0UM

Decimal Adjust Register for Addition

ADJBA Decimal Adjustment of Addition Result

[Instruction format] ADJBA

[Operation] Decimal Adjust Accumulator for Addition

[Operand]

None

[Flag]

ZACCY

×××

[Description]

• The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out

an operation having meaning only when the BCD (binary coded decimal) data is added and the addition result

is stored in the A register (in all other cases, the instruction carries out an operation having no meaning).

See the table below for the adjustment method.

• If the adjustment result shows that the A register contents are 0, the Z flag is set (1). In all other cases,

the Z flag is cleared (0).

Condition Operation

A3 to A0 ≤ 9A7 to A4 ≤ 9 and CY = 0 A ←A, CY ←0, AC ←0

AC = 0 A7 to A4 ≥ 10 or CY = 1 A ←A+01100000B, CY←1, AC ←0

A3 to A0 ≥ 10 A7 to A4 < 9 and CY = 0 A ←A+00000110B, CY ←0, AC ←1

AC = 0 A7 to A4 ≥ 9 or CY = 1 A ←A+01100110B, CY ←1, AC ←1

AC = 1 A7 to A4 ≤ 9 and CY = 0 A ←A+00000110B, CY ←0, AC ←0

A7 to A4 ≥ 10 or CY = 1 A←A+01100110B, CY ←1, AC ←0

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: