NEC 78K/0 Series BTCLR

114

CHAPTER 5 EXPLANATION OF INSTRUCTIONS

User's Manual U12326EJ4V0UM

Branch if True and Clear

BTCLR Conditional Branch and Clear by Bit Test (Byte Data Bit = 1)

[Instruction format] BTCLR bit, $addr16

[Operation] PC ← PC+b+jdisp8 if bit = 1, then bit ←0

[Operand]

Mnemonic Operand(bit,$addr16) b(Number of bytes)

BTCLR saddr.bit, $addr16 4

sfr.bit, $addr16 4

A.bit, $addr16 3

PSW.bit, $addr16 4

[HL].bit, $addr16 3

[Flag]

bit =PSW.bit In all other cases

Z AC CY Z AC CY

×××

[Description]

• If the 1st operand (bit) contents have been set (1), they are cleared (0) and branched to the address specified

by the 2nd operand.

If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent

instruction is executed.

• When the 1st operand (bit) is PSW.bit, the corresponding flag contents are cleared (0).

[Description example]

BTCLR PSW.0, $356H; When bit 0 (CY flag) of PSW is 1, the CY flag is cleared to 0 and branched to address

0356H (with the start of this instruction set in the range of addresses 02D4H to

03D3H).

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: