NEC 78K/0 Series RETI

CHAPTER 5 EXPLANATION OF INSTRUCTIONS

99

User's Manual U12326EJ4V0UM

Return from Interrupt

RETI Return from Hardware Vectored Interrupt

[Instruction format] RETI

[Operation] PCL←(SP),

PCH←(SP+1),

PSW ←(SP+2),

SP ←SP+3,

NMIS ← 0

[Operand]

None

[Flag]

ZACCY

RRR

[Description]

• This is a return instruction from the vectored interrupt.

• The data saved to the stack returns to the PC and the PSW, and the program returns from the interrupt service

routine.

• This instruction cannot be used for return from the software interrupt with the BRK instruction.

• None of interrupts are acknowledged between this instruction and the next instruction to be executed.

• The NMIS flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the RETI

instruction.

[Caution]

When the return from non-maskable interrupt servicing is performed by an instruction other than the RETI

instruction, the NMIS flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts)

except software interrupts can be acknowledged.

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: