CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
126 Users Manual U10676EJ3V0UM
(1) Timer counter mode registers (TM0, TM1, TM2)
A timer counter mode register (TMn) is an 8-bit register that controls the corresponding timer counter. Figures
6-26 to 6-28 show the formats of the various mode registers.
The timer counter mode register is set by an 8-bit memory manipulation instruction.
Bit 3 of this register is a timer start bit and can be manipulated in 1-bit units independently of the other bits.
This bit is automatically reset to 0 when the timer starts operating.
All the bits of the timer counter mode register are cleared to 0 when the RESET signal is asserted.
Examples1. To start timer in interval timer mode of CP = 5.86 kHz (at fX = 6.0 MHz)Note
SEL MB15 ; or CLR1 MBE
MOV XA, #01001100B
MOV TMn, XA ; TMn 4CH
2. To restart timer according to setting of timer counter mode register
SEL MB15 ; or CLR1 MBE
SET1 TMn.3 ; TMn.bit3 1
Note CP = 4.10 kHz when the
µ
PD754244 is operating at fx = 4.19 MHz.
CP = 977 kHz when the
µ
PD754144 is operating at fCC = 1.0 MHz.
Remark n = 0 to 2