NEC PD754144, PD754244 user manual - page 9

9
User’s Manual U10676EJ3V0UM
TABLE OF CONTENTS
CHAPTER 1 GENERAL ..................................................................................................................... 17
1.1 Functional Outline ............................................................................................................. 18
1.2 Ordering Information ......................................................................................................... 19
1.3 Differences Between Series Products ............................................................................ 19
1.4 Block Diagram .................................................................................................................... 20
1.5 Pin Configuration (Top View)............................................................................................ 21
CHAPTER 2 PIN FUNCTIONS .......................................................................................................... 24
2.1 Pin Functions of µ PD754244 ............................................................................................ 24
2.2 Description of Pin Functions ........................................................................................... 26
2.2.1 P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8)....................................................... 26
2.2.2 P70 to P73 (Port 7)................................................................................................................ 26
2.2.3 PTO0 to PTO2 ....................................................................................................................... 26
2.2.4 INT0........................................................................................................................................ 27
2.2.5 KR4 to KR7 ............................................................................................................................ 27
2.2.6 KRREN................................................................................................................................... 27
2.2.7 TH00 and TH01 ..................................................................................................................... 27
2.2.8 AVREF ...................................................................................................................................... 28
2.2.9 CL1 and CL2 ( µ PD754144 only)........................................................................................... 28
2.2.10 X1 and X2 ( µ PD754244 only) ............................................................................................... 28
2.2.11 RESET.................................................................................................................................... 28
2.2.12 IC ............................................................................................................................................ 29
2.2.13 VDD.......................................................................................................................................... 29
2.2.14 VSS .......................................................................................................................................... 29
2.3 Pin I/O Circuits ................................................................................................................... 30
2.4 Processing of Unused Pins.............................................................................................. 3 1
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP........................................... 32
3.1 Bank Configuration of Data Memory and Addressing Modes..................................... 32
3.1.1 Bank configuration of data memory...................................................................................... 32
3.1.2 Addressing mode of data memory........................................................................................ 34
3.2 Bank Configuration of General-Purpose Registers ...................................................... 45
3.3 Memory-Mapped I/O........................................................................................................... 50
CHAPTER 4 INTERNAL CPU FUNCTION ....................................................................................... 60
4.1 Function to Select MkI and MkII Modes.......................................................................... 60
4.1.1 Difference between MkI and MkII modes ............................................................................. 60
4.1.2 Setting stack bank select register (SBS).............................................................................. 61
4.2 Program Counter (PC)....................................................................................................... 62
4.3 Program Memory (ROM).................................................................................................... 63
4.4 Data Memory (RAM)........................................................................................................... 65
4.4.1 Configuration of data memory............................................................................................... 65
4.4.2 Specifying bank of data memory .......................................................................................... 66
4.5 General-Purpose Registers .............................................................................................. 69