CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
90 Users Manual U10676EJ3V0UM
Figure 6-2. P3n Configuration (n = 0 to 2)
Input buffer

MPX

Output latch
PM3n
PTOn
Output buffer
Input buffer
POGA bit 3
V
DD
Pull-up resistor
P-ch
P3n/PTOn

Internal bus

Figure 6-3. P33 Configuration
Input buffer

MPX

Output latch
PM33
Output buffer
Input buffer
POGA bit 3
VDD
Pull-up resistor
P-ch
P33

Internal bus