Main
Users Manual
PD754144, 754244
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NOTES FOR CMOS DEVICES
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Regional Information
components, host computers, power plugs, AC supply voltages, and so forth)
NEC Electronics America, Inc. (U.S.)
NEC Electronics Hong Kong Ltd.
NEC Electronics Shanghai, Ltd.
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INTRODUCTION
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LIST OF FIGURES (1/3)
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LIST OF FIGURES (2/3)
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LIST OF TABLES
CHAPTER 1 GENERAL
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1.1 Functional Outline
1.2 Ordering Information
Part Number Package
PD754141GS--BA5 20-pin plastic SOP (7.62 mm (300))
PD754141GS--GJG 20-pin plastic SSOP (7.62 mm (300))
PD754244GS--BA5 20-pin plastic SOP (7.62 mm (300))
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1.4 Block Diagram
CHAPTER 1 GENERAL
1.5 Pin Configuration (Top View)
Pin configuration of
IC: Internally Connected (Directly connect to VDD.)
PD754144 20-pin plastic SOP (7.62 mm (300))
PD754144GS--BA5 20-pin plastic SSOP (7.62 mm (300))
Pin configuration of
PD754244 20-pin plastic SOP (7.62 mm (300))
IC: Internally Connected (Directly connect to VDD.)
PD754244GS--BA5 20-pin plastic SSOP (7.62 mm (300))
PD754244GS--GJG
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CHAPTER 2 PIN FUNCTIONS 2.1 Pin Functions of
PD754244
Table 2-1. Pin Functions of Digital I/O Ports
Table 2-2. Functions of Non-Port Pins
Note Circled characters indicate Schmitt triggered input.
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2.2 Description of Pin Functions
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PD754244
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CHAPTER 2 PIN FUNCTIONS
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2.3 Pin I/O Circuits
The following diagrams show the I/O circuits of the pins of the
PD754244. Note that in these diagrams the I/ O circuits have been slightly simplified.
2.4 Processing of Unused Pins
Table 2-3. Recommended Connection of Unused Pins
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
3.1 Bank Configuration of Data Memory and Addressing Modes
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Figure 3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode
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Figure 3-3. Updating Address of Static RAM
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3.2 Bank Configuration of General-Purpose Registers
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Figure 3-5. Configuration of General-Purpose Registers (4-Bit Processing)
Figure 3-6. Configuration of General-Purpose Registers (8-Bit Processing)
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3.3 Memory-Mapped I/O
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Figure 3-7.
PD754244 I/O Map (2/8)
Figure 3-7.
PD754244 I/O Map (3/8)
Figure 3-7.
PD754244 I/O Map (4/8)
Figure 3-7.
PD754244 I/O Map (5/8)
Figure 3-7.
PD754244 I/O Map (6/8)
Note These are not registered as reserved words.
Figure 3-7.
PD754244 I/O Map (7/8)
Figure 3-7.
PD754244 I/O Map (8/8)
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CHAPTER 4 INTERNAL CPU FUNCTION 4.1 Function to Select MkI and MkII Modes
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4.2 Program Counter (PC) 12 bits
4.3 Program Memory (ROM) 4096 8 bits
CHAPTER 4 INTERNAL CPU FUNCTION
Figure 4-3. Program Memory Map
4.4 Data Memory (RAM) ... 128 words 4 bits
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Figure 4-4. Data Memory Map
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4.5 General-Purpose Registers ... 8 4 bits 4 banks
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4.6 Accumulator
4.7 Stack Pointer (SP) and Stack Bank Select Register (SBS)
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Figure 4-9. Data Saved to Stack Memory (MkI Mode)
Figure 4-10. Data Restored from Stack Memory (MkI Mode)
Figure 4-11. Data Saved to Stack Memory (MkII Mode)
Figure 4-12. Data Restored from Stack Memory (MkII Mode)
Note The contents of PSW other than MBE and RBE are not saved or restored. Remark *: Undefined
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4.8 Program Status Word (PSW) ... 8 Bits
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4.9 Bank Select Register (BS)
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CHAPTER 5 EEPROM
5.1 EEPROM Configuration
5.2 EEPROM Features
5.3 EEPROM Write Control Register (EWC)
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5.4 Interrupt Related to EEPROM Control
5.5 EEPROM Manipulation Method
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5.6 Cautions on EEPROM Writing
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Ports
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Figure 6-2. P3n Configuration (n = 0 to 2)
MPX
Internal bus
Figure 6-3. P33 Configuration
MPX
Figure 6-4. P60 Configuration
Figure 6-5. P61 Configuration
Figure 6-6. P62 Configuration
Figure 6-7. P63 Configuration
Figure 6-8. P7n Configuration (n = 0 to 3)
Figure 6-9. P80 Configuration
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Table 6-2. I/O Pin Manipulation Instructions
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Table 6-3. Operation When I/O Port Is Manipulated
Remark <1> : Indicates two addressing modes: PORTn, bit and PORTn.@L.
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0 1 2
(b) When data is loaded by 2-machine-cycle instruction
(c) When data is latched by 1-machine-cycle instruction
Instruction execution
Manipulation instruction
Output latch (output pin)
Figure 6-13. ON Timing of Internal Pull-up Resistor Connected via Software
6.2 Clock Generator
PD754144 (RC oscillation)
Internal bus
Figure 6-14. Block Diagram of Clock Generator (2/2) (b)
PD754244 Crystal/Ceramic Oscillation
Internal bus
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Figure 6-15. Format of Processor Clock Control Register
Remark fCC and fX: System clock oscillation frequency
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PD754144
PD754244
PD754144
PD754244
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PD754144
PD754144
PD754244
PD754244
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6.3 Basic Interval Timer/Watchdog Timer
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Figure 6-21. Format of Basic Interval Timer Mode Register
Note In the
s at 1.0 MHz).
PD754144, wait time is always fixed to 29/fCC (512
PD754244 only, wait time is selectable when standby mode is released. In the
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Example To use the
PD754144, it is 32.8 ms at fCC = 1.0 MHz.
Note It is 7.81 ms when the
(After that, set bit 3 of BTM to 1 every 5.46 ms.)
PD754244 is operating at fX = 4.19 MHz. In the case of the
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6.4 Timer Counter
Figure 6-23. Block Diagram of Timer Counter (Channel 0)
Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0.
Figure 6-24. Block Diagram of Timer Counter (Channel 1)
Figure 6-25. Block Diagram of Timer Counter (Channel 2)
Caution Be sure to clear bit 7 to 0 when setting data to TC2.
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Figure 6-26. Format of Timer Counter Mode Register (Channel 0)
Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (1/2)
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Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (1/2)
Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (2/2)
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Figure 6-31. Setting of Timer Counter Mode Register (1/3) (a) Timer counter (channel 0)
Note Be sure to clear bits 0 and 1 to 0 when setting data to TM0.
Figure 6-31. Setting of Timer Counter Mode Register (2/3) (b) Timer counter (channel 1)
Figure 6-31. Setting of Timer Counter Mode Register (3/3) (c) Timer counter (channel 2)
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(b)
PD754244: at 4.19 MHz 8-bit timer counter (channel 0)
8-bit timer counter (channel 1)
PD754144: at 1.0 MHz 8-bit timer counter (channel 0)
8-bit timer counter (channel 1)
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Figure 6-34. Configuration When Timer Counter Operates
Figure 6-35. Count Operation Timing
Remark m: Set value of timer counter modulo register n : 0 to 2
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Figure 6-36. Setting of Timer Counter Mode Register
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Figure 6-38. PWM Pulse Generator Operating Configuration
012 i11012 k1k0123
Count pulse (CP) Timer counter count register (T2) TOUT F/F Set Timer start command
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Figure 6-40. Setting of Timer Counter Mode Registers
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Figure 6-42. Configuration When Timer Counter Operates
Figure 6-43. Timing of Count Operation
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Figure 6-44. Setting of Timer Counter Mode Register (n = 1, 2)
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Figure 6-47. Configuration in Carrier Generator Mode
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6.5 Programmable Threshold Port (Analog Input Port)
Figure 6-49. Block Diagram of Programmable Threshold Port
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6.6 Bit Sequential Buffer ... 16 Bits
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS
7.1 Configuration of Interrupt Controller
Figure 7-1. Block Diagram of Interrupt Controller
Selector
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7.2 Types of Interrupt Sources and Vector Table
The
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7.3 Hardware Controlling Interrupt Function
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Figure 7-3. Interrupt Priority Select Register
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Figure 7-4. Configuration of INT0
Remark tSMP = tCY or 64/fX
Figure 7-6. Format of INT0 Edge Detection Mode Register (IM0)
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7.4 Interrupt Sequence
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7.5 Nesting Control of Interrupts
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7.6 Servicing of Interrupts Sharing Vector Address
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7.7 Machine Cycles Until Interrupt Servicing
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7.8 Effective Usage of Interrupts
7.9 Application of Interrupt
(1) Enabling or disabling interrupt
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(4) Executing pending interrupt - interrupt input while interrupts are disabled -
(5) Executing pending interrupt - two interrupts with lower priority occur simultaneously -
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7.10 Test Function
Figure 7-10. Block Diagram of KR4 to KR7
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CHAPTER 8 STANDBY FUNCTION
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8.1 Settings and Operating Statuses of Standby Mode
Table 8-1. Operating Statuses in Standby Mode
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8.2 Releasing Standby Mode
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8.3 Operation After Release of Standby Mode
8.4 Application of Standby Mode
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CHAPTER 9 RESET FUNCTION 9.1 Configuration and Operation of Reset Function
Internal bus
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9.2 Watchdog Flag (WDF), Key Return Flag (KRF)
CHAPTER 9 RESET FUNCTION
Figure 9-4. KRF Operation in Generating Each Signal
CHAPTER 10 MASK OPTIONS
10.1 Pin Mask Options
10.2 Oscillation Stabilization Wait Time Mask Option
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CHAPTER 11 INSTRUCTION SET
11.1 Unique Instructions
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11.2 Instruction Set and Operation
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Note Set 0 to the B register.
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PCDE 2 3
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11.3 Opcode of Each Instruction
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11.4 Instruction Function and Application
MOV A, #n4
MOV reg1, #n4
MOV XA, #n8
MOV HL, #n8
MOV rp2, #n8
MOV A, @HL
MOV A, @HL+
MOV A, @HL
MOV A, @rpa1
MOV XA, @HL
MOV @HL, A
MOV @HL, XA
MOV A, mem
MOV XA, mem
MOV mem, A
MOV mem, XA
MOV A, reg
MOV XA, rp
MOV reg1, A
XCH A, @HL
XCH A, @HL+
XCH A, @HL
XCH A, @rpa1
XCH XA, @HL
XCH A, mem
XCH XA, mem
XCH A, reg1
XCH XA, rp
MOV XA, @PCDE
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MOVT XA, @PCXA
MOVT XA, @BCDE
MOVT XA, @BCXA
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ADDS A, #n4
ADDS XA, #n8
ADDS A, @HL
ADDS XA, rp
ADDS rp1, XA
ADDC A, @HL
ADDC XA, rp
ADDC rp1, XA
SUBS A, @HL
SUBS XA, rp
SUBS rp1, XA
SUBC A, @HL
SUBC XA, rp
SUBC rp1, XA
AND A, #n4
AND A, @HL
AND XA, rp
AND rp1, XA
OR A, #n4
OR A, @HL
OR XA, rp
OR rp1, XA
XOR A, #n4
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11.4.5 Accumulator manipulation instructions
RORC A
NOT A
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BR addr
BR addr1
BRA !addr1
BR !addr
BR $addr
BR $addr1
BRCB !caddr
BR PCDE
BR PCXA
BR BCDE
BR BCXA
TBR addr
CALLA !addr1
CALL !addr
CALLF !faddr
TCALL !addr
RET
RETS
RETI
PUSH rp
PUSH BS
POP rp
POP BS
EI
EI IE
DI
DI IE
IN A, PORTn
OUT PORTn, A
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SEL RBn
SEL MBn
GETI taddr
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available to support development of systems using the
PD754244. The following table shows the system configuration of the in-circuit emulators.
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Development Tool Configuration
APPENDIX B ORDERING MASK ROM
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APPENDIX C INSTRUCTION INDEX C.1 Instruction Index (By Function)
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C.2 Instruction Index (Alphabetical Order)
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APPENDIX D HARDWARE INDEX
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APPENDIX E REVISION HISTORY
