NEC PD754144, PD754244 - page 151

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
151
User’s Manual U10676EJ3V0UM
6.4.4 Operation in 16-bit timer counter mode
In this mode, two timer counter channels, 1 and 2, are used in combination to implement 16-bit programmable
interval timer or event timer operation.
(1) Register setting
In the 16-bit timer counter mode, the following seven registers are used.
• Timer counter mode registers TM1 and TM2
• Timer counter control register TC2Note
• Timer count registers T1 and T2
• Timer count modulo registers TMOD1 and TMO2
Note Timer counter channel 1 uses the timer counter output enable flag (TOE1).
(a) Timer counter mode registers (TM1 and TM2)
In the 16-bit timer counter mode, TM1 and TM2 are set as shown in Figure 6-40 (for the formats of TM1
and TM2, refer to Figure 6-27 Format of Timer Counter Mode Register (Channel 1) and Figure 6-
28 Format of Timer Counter Mode Register (Channel 2)).
TM1 and TM2 are manipulated by an 8-bit manipulation instruction. Bit 3 of these registers is a timer start
command bit that can be manipulated in 1-bit units and is automatically cleared to 0 when the timer starts
operating.
TM1 and TM2 are cleared to 00H when the internal reset signal is asserted.
The flags shown by a solid line in Figure 6-39 are used in the 16-bit timer counter mode.
Do not use the flags shown by a dotted line in the 16-bit timer counter mode (clear these flags to 0).