CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
142 User’s Manual U10676EJ3V0UM
(3) Timer counter operation (8-bit)
The timer counter operates as follows.
Figure 6-34 shows the configuration when the timer counter operates.
<1> The count pulse (CP) is selected by the timer counter mode register (TMn) and is input to the timer
counter count register (Tn).
<2> The contents of Tn are compared with those of the modulo register (TMODn). When the contents of
these registers match, a match signal is generated, and the interrupt request flag (IRQTn) is set. At
the same time, the timer out flip/flop (TOUT F/F) is inverted.
Figure 6-35 shows the timing of the timer counter operation.
The timer counter operation is usually started using the following procedure.
<1> Set the number of counts to TMODn.
<2> Sets the operation mode, count pulse, and start command to TMn.
Caution Set a value other than 00H to the timer counter modulo register (TMODn).
To use the timer counter output pin (PTOn), set the P3n pin as follows.
<1> Clear the output latch of P3n.
<2> Set port 3 in the output mode.
<3> Disconnect the on-chip pull-up resistor from port 3.
<4> Set the timer internal counter output enable flag (TOEn) to 1.
Remark n = 0 to 2