CHAPTER 7 INTERRUPT AND TEST FUNCTIONS
190 User’s Manual U10676EJ3V0UM
7.3 Hardware Controlling Interrupt Function(1) Interrupt request flag and interrupt enable flag
The
µ
PD754244 has the following six interrupt request flags (IRQ×××) corresponding to the respective interrupt
sources.
INT0 interrupt request flag (IRQ0)
BT interrupt request flag (IRQBT)
EEPROM interrupt request flag (IRQEE)
Timer counter 0 interrupt request flag (IRQT0)
Timer counter 1 interrupt request flag (IRQT1)
Timer counter 2 interrupt request flag (IRQT2)
Each interrupt request flag is set to “1” when the corresponding interrupt request is generated, and is
automatically cleared to “0” when the interrupt servicing is executed. However, because IRQT1 and IRQT2
share the vector address, these flags are cleared differently from the other flags (refer to 7.6 Servicing of
Interrupts Sharing Vector Address).
The
µ
PD754144 also has six interrupt enable flags (IE×××) corresponding to the respective interrupt request
flags.
INT0 interrupt enable flag (IE0)
BT interrupt enable flag (IEBT)
EEPROM interrupt enable flag (IEEE)
Timer counter 0 interrupt enable flag (IET0)
Timer counter 1 interrupt enable flag (IET1)
Timer counter 2 interrupt enable flag (IET2)
The interrupt enable flag enables the corresponding interrupt when it is “1”, and disables the interrupt when
it is “0”.
If an interrupt request flag is set and the corresponding interrupt enable flag enables the interrupt, a vector
interrupt (VRQn: n = 1, 2, or 5 to 7) occurs. This signal is also used to release the standby mode.
The interrupt request flags and interrupt enable flags are manipulated by a bit manipulation or 4-bit
manipulation instruction. When a bit manipulation instruction is used, the flags can be directly manipulated,
regardless of the setting of MBE. The interrupt enable flags are manipulated by the EI IE××× and DI IE×××
instructions. To test an interrupt request flag, the SKTCLR instruction is usually used.
Example
EI IE0 ; Enables INT0
DI IET1 ; Disables INTT1
SKTCLR IRQBT ; Skips and clears if IRQBT is 1
When an interrupt request flag is set by an instruction, a vector interrupt is executed even if an interrupt does
not occur, in the same manner as when the interrupt occurs.
The interrupt request flags and interrupt enable flags are cleared to “0” when the RESET signal is asserted,
disabling all the interrupts.