NEC Figure 7-1. Block Diagram of Clock Generator

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CHAPTER 7 CLOCK GENERATOR
Figure 7-1. Block Diagram of Clock Generator
Subsystem
Clock
Oscillator
Main
System
Clock
Oscillator
X2
X1
XT2
XT1/P07
FRC
STOP
MCC FRC CLS CSS
PCC2 PCC1
Internal Bus
Standby
Control
Circuit
To INTP0
Sampling Clock
2
f
XX
2
2
f XX
2
3
f XX
2
4
f XX
Prescaler
Clock to
Peripheral
Hardware
Prescaler
Oscillation Mode
Selection Register
Watch Timer,
Clock Output
Function
f
XX
CPU Clock
(f
CPU )
Wait
Control
Circuit
Scaler
Selector
f X
f XT
2
f
X
MCS
Processor Clock Control Register
2
f
XT
PCC0
3
Selector
1/2