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CHAPTER 19 SERIAL INTERFACE CHANNEL 2
RxD (Input)
INTSR
INTSER (when Framing or
Overrun Error is Generated)
INTSER (when Parity Error
is Generated)
D0
T1 T2
D1 D2 D6 D7 STOP
START
Parity
Figure 19-15. Period that Reading Receive Buffer Register Is Prohibited
T1 : The amount of time for one unit of data sent in the baud rate selected with the baud
rate generator control register (BRGC) (1/baud rate)
T2 : The amount of time for 2 clocks of 5-bit counter source clock (fSCK) selected with
BRGC
Example of countermeasures
An example of the countermeasures is shown below.
[Condition]
fX = 5.0 MHz
Processor clock control register (PCC) = 00H
Oscillation mode selection register (OSMS) = 01H
Baud rate generator control register (BRGC) = B0H (when 2400 bps is selected for baud rate)
TCY = 0.4
µ
s (tCY = 0.2
µ
s)
1
T1 = = 416.7
µ
s
2400
T2 = 12.8 x 2 = 25.6
µ
s
T1 + T2 = 2212 (clock)
tCY