293
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
ยต
PD78058F SUBSERIES)
Serial Interface Channel 0 Serial Clock Selection
TCL33TCL32 TCL31 TCL30
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2
fXX/22
fXX/23
fXX/24
fXX/25
fXX/26
fXX/27
fXX/28
Setting prohibited
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
Other than above Setting prohibited
Serial Interface Channel 1 Serial Clock Selection
TCL37TCL36 TCL35 TCL34
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2
fXX/22
fXX/23
fXX/24
fXX/25
fXX/26
fXX/27
fXX/28
Setting prohibited
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
Other than above Setting prohibited
65432107
Symbol
TCL3 TCL37TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R/W
Address After Reset R/W
MCS = 1 MCS = 0
MCS = 1 MCS = 0
Figure 16-3. Timer Clock Select Register 3 FormatCaution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fXX : Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.