27
LIST OF FIGURES (5/8)Figure No. Title Page
16-27 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 325
16-28 Command Transmission from Master Device to Slave Device......................................................... 326
16-29 Data Transmission from Master Device to Slave Device.................................................................. 327
16-30 Data Transmission from Slave Device to Master Device.................................................................. 328
16-31 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 331
16-32 2-Wire Serial I/O Mode Timings........................................................................................................ 334
16-33 RELT and CMDT Operations............................................................................................................ 335
16-34 SCK0/P27 Pin Configuration ............................................................................................................ 336
17-1 Serial Bus Configuration Example Using I2C Bus............................................................................. 339
17-2 Serial Interface Channel 0 Block Diagram........................................................................................ 341
17-3 Timer Clock Select Register 3 Format.............................................................................................. 346
17-4 Serial Operating Mode Register 0 Format ........................................................................................ 348
17-5 Serial Bus Interface Control Register Format................................................................................... 349
17-6 Interrupt Timing Specify Register Format......................................................................................... 351
17-7 3-Wire Serial I/O Mode Timings........................................................................................................ 356
17-8 RELT and CMDT Operations............................................................................................................ 356
17-9 Circuit of Switching in Transfer Bit Order.......................................................................................... 357
17-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 358
17-11 2-Wire Serial I/O Mode Timings........................................................................................................ 361
17-12 RELT and CMDT Operations............................................................................................................ 362
17-13 Example of Serial Bus Configuration Using I2C Bus......................................................................... 363
17-14 I2C Bus Serial Data Transfer Timing................................................................................................. 364
17-15 Start Condition .................................................................................................................................. 365
17-16 Address............................................................................................................................................. 365
17-17 Transfer Direction Specification........................................................................................................ 365
17-18 Acknowledge Signal ......................................................................................................................... 366
17-19 Stop Condition .................................................................................................................................. 366
17-20 Wait Signal........................................................................................................................................ 367
17-21 Pin Configuration .............................................................................................................................. 372
17-22 Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)............. 374
17-23 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)............. 377
17-24 Start Condition Output ...................................................................................................................... 380
17-25 Slave Wait Release (Transmission).................................................................................................. 381
17-26 Slave Wait Release (Reception)....................................................................................................... 382
17-27 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385
17-28 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385
17-29 Logic Circuit of SCL Signal ............................................................................................................... 386
18-1 Serial Interface Channel 1 Block Diagram........................................................................................ 389
18-2 Timer Clock Select Register 3 Format.............................................................................................. 392
18-3 Serial Operating Mode Register 1 Format ........................................................................................ 393
18-4 Automatic Data Transmit/Receive Control Register Format............................................................. 394