Main
Users Manual
PD78058F , 78058FY Subseries
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NOTES FOR CMOS DEVICES
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Regional Information
MAJOR REVISIONS IN THIS EDITION
The mark shows major revised points.
PREFACE
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Chapter Organization This manual divides the descriptions for the
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Development Tool Documents (Users Manuals)
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LIST OF FIGURES (1/8)
LIST OF FIGURES (2/8)
LIST OF FIGURES (3/8)
LIST OF FIGURES (4/8)
LIST OF FIGURES (5/8)
LIST OF FIGURES (6/8)
LIST OF FIGURES (7/8)
LIST OF FIGURES (8/8)
LIST OF TABLES (1/3)
LIST OF TABLES (2/3)
LIST OF TABLES (3/3)
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CHAPTER 1 OUTLINE (
1.1 Features
1.2 Applications
1.3 Ordering Information
1.4 Quality Grade
Remark indicates ROM code suffix.
1.5 Pin Configuration (Top View)
(1) Normal operating mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm)
PD78P058F.
PD78056FGC--3B9, 78058FGC--3B9, 78058FGC(A)--3B9, 78P058FGC-3B9
PD78056FGC--8BT, 78058FGC--8BT, 78P058FGC-8BT 80-pin plastic TQFP (Fine pitch) (12 12 mm)
Pin Identifications
(2) PROM programming mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm)
PD78P058FGC-3B9
PD78P058FGC-8BT
1.6 78K/0 Series Expansion
The 78K/0 Series expansion is shown below. The names in frames are subseries.
Note Under planning
The differences between the major functions of each subseries are shown below.
Notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel
1.7 Block Diagram
PD78P058F.
1.8 Outline of Function
1.9 Differences Between the
PD78058F and
PD78058F(A)
PD78058F and
Table 1-1. Differences Between the
1.10 Mask Options
CHAPTER 2 OUTLINE (
2.1 Features
2.2 Applications
2.3 Ordering Information
2.4 Quality Grade
Note Under development Remark indicates ROM code suffix.
2.5 Pin Configuration (Top View)
(1) Normal operating mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm)
PD78P058FY.
PD78056FYGC--3B9, 78058FYGC--3B9, 78058FYGC(A)--3B9,
PD78P058FYGC-3B9 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm)
Pin Identifications
(2) PROM programming mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm)
PD78P058FYGC-3B9
PD78P058FYGC-8BT
2.6 78K/0 Series Expansion
The 78K/0 Series expansion is shown below. The names in frames are subseries.
Note Under planning
The differences between the major functions of each subseries are shown below.
Remark Functions other than the serial interface are common with Subseries without the Y.
2.7 Block Diagram
PD78P058FY.
2.8 Outline of Function
Note Under development for the
2.9 Differences Between the
PD78058FY(A)
PD78058FY and
Table 2-1. Differences Between the
PD78P058FY only.
2.10 Mask Options
CHAPTER 3 PIN FUNCTION (
3.1 Pin Function List
3.1.1 Normal operating mode pins (1) Port pins (1/3)
(1) Port pins (2/3)
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(2) Non-port pins (1/2)
(2) Non-port pins (2/2)
Cautions 1. The AVDD pin is used in common as the power supply for the A/D converter and port. If
3.1.2 PROM programming mode pins (PROM versions only)
3.2 Description of Pin Functions
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3.3 Input/output Circuits and Recommended Connection of Unused Pins
Table 3-1. Pin Input/Output Circuit Types (2/2)
CHAPTER 3 PIN FUNCTION (
Figure 3-1. List of Pin Input/Output Circuit (1/2)
Figure 3-1. List of Pin Input/Output Circuit (2/2)
CHAPTER 4 PIN FUNCTION (
4.1 Pin Function List
4.1.1 Normal operating mode pins (1) Port pins (1/3)
(1) Port pins (2/3)
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(2) Non-port pins (1/2)
(2) Non-port pins (2/2)
4.1.2 PROM programming mode pins (PROM versions only)
4.2 Description of Pin Functions
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4.3 Input/output Circuits and Recommended Connection of Unused Pins
Table 4-1. Pin Input/Output Circuit Types (2/2)
Figure 4-1. List of Pin Input/Output Circuit (1/2)
Figure 4-1. List of Pin Input/Output Circuit (2/2)
CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces
64-Kbyte memory spaces can be accessed in the
PD78058F, 78058FY Subseries. Figures 5-1 to 5-3 show memory maps. Figure 5-1. Memory Map (
PD78056F, 78056FY)
Figure 5-2. Memory Map (
PD78058F, 78058FY)
CHAPTER 5 CPU ARCHITECTURE
Figure 5-3. Memory Map (
PD78P058F,
PD78P058FY)
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Figure 5-5. Data Memory Addressing (
PD78058F, 78058FY)
Figure 5-6. Data Memory Addressing (
PD78P058F, 78P058FY)
5.2 Processor Registers
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Figure 5-11. Data to Be Reset from Stack Memory
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CHAPTER 5 CPU ARCHITECTURE
Figure 5-12. General Register Configuration (a) Absolute Name
(b) Function Name
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Table 5-3. Special-Function Register List (1/3)
Table 5-3. Special-Function Register List (2/3)
PD78058F, 78058FY, 78P058F and 78P058FY.
Note This register is provided only in the
Table 5-3. Special-Function Register List (3/3)
PD78058F, 78058FY, 78P058F, and 78P058FY.
PD78058F, 78058FY: CFH,
PD78056F, 78056FY: CCH,
PD78P058F, 78P058FY: CFH 3. This register is provided only in the
5.3 Instruction Address Addressing
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5.4 Operand Address Addressing
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CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions
The
Table 6-1. Port Functions (
PD78058F Subseries) (1/2)
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Table 6-2. Port Functions (
PD78058FY Subseries) (1/2)
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6.2 Port Configuration
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6.3 Port Function Control Registers
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CHAPTER 6 PORT FUNCTIONS
Figure 6-19. Port Mode Register Format
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6.4 Port Function Operations
6.5 Selection of Mask Option
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CHAPTER 7 CLOCK GENERATOR
Figure 7-1. Block Diagram of Clock Generator
Selector
7.3 Clock Generator Control Register
Figure 7-3. Processor Clock Control Register Format
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7.4 System Clock Oscillator
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7.5 Clock Generator Operations
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7.6 Changing System Clock and CPU Clock Settings
Table 7-3. Maximum Time Required for CPU Clock Switchover
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Overview of the
PD78058F and 78058FY Subseries On-Chip Timers
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8.2 16-Bit Timer/Event Counter Functions
Note Refer to the Figure 21-1 Basic Configuration of Interrupt Function.
8.3 16-Bit Timer/Event Counter Configuration
Selector
Note 2
Figure 8-1. 16-Bit Timer/Event Counter Block Diagram
Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram
Remark The circuitry enclosed by the dotted line is the output control circuit.
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8.4 16-Bit Timer/Event Counter Control Registers
Figure 8-3. Timer Clock Selection Register 0 Format
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Figure 8-6. 16-Bit Timer Output Control Register Format
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8.5 16-Bit Timer/Event Counter Operations
Figure 8-11. Interval Timer Configuration Diagram
Figure 8-12. Interval Timer Operation Timings
Remark Interval time = (N + 1) t : N = 0001H to FFFFH.
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capture/compare register 00 (CR00) value
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Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
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Figure 8-27. External Event Counter Configuration Diagram
Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified)
Caution When reading the external event counter count value, TM0 should be read.
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Count Clock TM0 Count Value CR00 INTTM00 TO0 Pin Output
0000 0001 0002 N-1 N 0000 0001 0002 N-1 N 0000 N
Figure 8-30. Square-Wave Output Operation Timing
Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges
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Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger
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8.6 16-Bit Timer/Event Counter Operating Precautions
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9.2 8-Bit Timer/Event Counter Configuration
Figure 9-1. 8-Bit Timer/Event Counter Block Diagram
Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
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Figure 9-4. Timer Clock Select Register 1 Format
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.
6. Figures in parentheses apply to operation with fX = 5.0 MHz
3. TI1 : 8-bit timer register 1 input pin 4. TI2 : 8-bit timer register 2 input pin
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9.4 8-Bit Timer/Event Counter Operation
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Figure 9-13. Square-Wave Output Operation Timing
9.5 Cautions on 8-Bit Timer/Event Counters
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CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions
10.2 Watch Timer Configuration
10.3 Watch Timer Control Registers
Figure 10-1. Watch Timer Block Diagram
Figure 10-2. Timer Clock Select Register 2 Format
4. : Don't care
CHAPTER 10 WATCH TIMER
10.4 Watch Timer Operations
CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions
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11.2 Watchdog Timer Configuration
Control register
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Figure 11-2. Timer Clock Select Register 2 Format
4. : Don't care
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11.4 Watchdog Timer Operations
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12.2 Clock Output Control Circuit Configuration
12.3 Clock Output Function Control Registers
Figure 12-3. Timer Clock Select Register 0 Format
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions
13.2 Buzzer Output Control Circuit Configuration
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
Figure 13-2. Timer Clock Select Register 2 Format
4. : don't care
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CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions
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Figure 14-1. A/D Converter Block Diagram
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14.3 A/D Converter Control Registers
Figure 14-2. A/D Converter Mode Register Format
Notes 1. Set so that the A/D conversion time is 19.1
s or more. 2. Setting prohibited because A/D conversion time is less than 19.1
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14.4 A/D Converter Operations
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14.5 A/D Converter Cautions
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CHAPTER 15 D/A CONVERTER
15.2 D/A Converter Configuration
Register
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15.3 D/A Converter Control Registers
15.4 Operations of D/A Converter
15.5 Cautions Related to D/A Converter
PD78058F, 78058FY
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
16.1 Serial Interface Channel 0 Functions
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16.2 Serial Interface Channel 0 Configuration
Figure 16-2. Serial Interface Channel 0 Block Diagram
Remark Output Control performs selection between CMOS output and N-ch open-drain output.
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Figure 16-3. Timer Clock Select Register 3 Format
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
(Continued)
3. Can be used freely as port function.
PMXX : Port Mode Register
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Figure 16-5. Serial Bus Interface Control Register Format (1/2)
Figure 16-5. Serial Bus Interface Control Register Format (2/2)
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16.4 Serial Interface Channel 0 Operations
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3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
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(b) Serial bus interface control register (SBIC)
The shaded area is used in the SBI mode.
(Continued)
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Figure 16-21. RELT and CMDD Operations (Slave)
Figure 16-22. ACKT Operation
Caution Do not set ACKT before termination of transfer.
Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer
(b) When set after completion of transfer
(d) When ACKE = 1 period is short
(c) When ACKE = 0 upon completion of transfer
Figure 16-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0
(b) When ACK signal is output after 9th clock of SCK0
Figure 16-25. BSYE Operation
(c) Clear timing when transfer start is instructed in BUSY
SCK0 D0 READY
Table 16-3. Various Signals in SBI Mode (1/2)
Table 16-3. Various Signals in SBI Mode (2/2)
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Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1)
Figure 16-28. Command Transmission from Master Device to Slave Device
Figure 16-29. Data Transmission from Master Device to Slave Device
Figure 16-30. Data Transmission from Slave Device to Master Device
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3. Be sure to set WUP to 0 when the 2-wire serial I/O mode. 4. When CSIE0 = 0, COI becomes 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
17.1 Serial Interface Channel 0 Functions
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17.2 Serial Interface Channel 0 Configuration
Figure 17-2. Serial Interface Channel 0 Block Diagram
Remark Output Control performs selection between CMOS output and N-ch open-drain output.
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Figure 17-3. Timer Clock Select Register 3 Format
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
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Figure 17-4. Serial Operating Mode Register 0 Format
Figure 17-5. Serial Bus Interface Control Register Format (1/2)
Remark CSIE0: Bit 7 of Serial Operation Mode Register 0 (CSIM0)
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Notes 1. Bit 6 (CLD) is a read-only bit. 2. When not using the I2C mode, set CLC to 0.
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17.4 Serial Interface Channel 0 Operations
3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
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(a) Serial operating mode register 0 (CSIM0)
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode. 4. When CSIE0=0, COI becomes 0.
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(Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address
(Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
(Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition
(Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address
(Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
(Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions
18.2 Serial Interface Channel 1 Configuration
Figure 18-1. Serial Interface Channel 1 Block Diagram
/2
/2 to f
f
Timer Clock Select Register 3
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Figure 18-2. Timer Clock Select Register 3 Format
Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand.
4. Figures in parentheses apply to operation with fX = 5.0 MHz
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2628 0.5
36
1.5
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4)
Minimum = (n+1) + + Maximum = (n+1) + +
2. Zero must be set in bits 5 and 6.
2628 0.5
2636 1.5
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4)
2628 f 2636 f
0.5
1.5
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4)
2628 0.5
2636 1.5
18.4 Serial Interface Channel 1 Operations
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2. Zero must be set in bits 5 and 6.
28 0.5 fXX fSCK
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Figure 18-9. Basic Transmission/Reception Mode Flowchart
TRF: Bit 3 of automatic data transmit/receive control register (ADTC)
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(c) Completion of transmission/reception
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Figure 18-12. Basic Transmission Mode Flowchart
TRF: Bit 3 of automatic data transmit/receive control register (ADTC)
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(c) Completion of transmission
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Figure 18-15. Repeat Transmission Mode Flowchart
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(c) 7th byte transmission point
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions
19.2 Serial Interface Channel 2 Configuration
to f
/2
Figure 19-1. Serial Interface Channel 2 Block Diagram
Note See Figure 19-2 for the baud rate generator configuration.
Figure 19-2. Baud Rate Generator Block Diagram
to f
/2
TPS0 to TPS3 SCK
ASCK/SCK2/P72 4
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19.3 Serial Interface Channel 2 Control Registers
Figure 19-4. Asynchronous Serial Interface Mode Register Format
(2) 3-wire Serial I/O Mode
Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode
(3) Asynchronous Serial Interface Mode
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Figure 19-6. Baud Rate Generator Control Register Format (1/2)
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19.4 Serial Interface Channel 2 Operation
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(d) Baud rate generator control register (BRGC)
(continued)
fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14)
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When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
(c) Baud rate generator control register (BRGC)
fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14)
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[Example]
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20.2 Real-Time Output Port Configuration
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20.3 Real-Time Output Port Control Registers
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21.2 Interrupt Sources and Configuration
Table 21-1. Interrupt Source List (2/2)
Figure 21-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
(B) Internal maskable interrupt
(C) External maskable interrupt (INTP0)
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21.3 Interrupt Function Control Registers
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
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Figure 21-6. External Interrupt Mode Register 1 Format
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21.4 Interrupt Servicing Operations
TMIF4: Watchdog Timer Interrupt Request Flag
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Figure 21-13. Interrupt Request Acknowledge Processing Algorithm
IE=1?
Start IF=1? MK=0? PR=0?
IE=1? ISP=1?
Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time)
f
Remark 1 clock : (fCPU: CPU clock)
1
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21.5 Test Functions
Caution Be sure to set bits 3 through 6 to 1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions
PD78056F and 78056FY, and of the
PD78P058F and 78P058FY when the internal PROM is 48 Kbytes.
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
Figure 22-1. Memory Map When Using External Device Expansion Function (2/2) (b)
(c)
22.2 External Device Expansion Function Control Register
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22.3 External Device Expansion Function Timing
Figure 22-4. Instruction Fetch from External Memory
Figure 22-5. External Memory Read Timing
Figure 22-6. External Memory Write Timing
Figure 22-7. External Memory Read Modify Write Timing
CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration
STOP Mode Clear X1 Pin Voltage Waveform V
a
CHAPTER 23 STANDBY FUNCTION
23.2 Standby Function Operations
Notes 1. Including when external clock is not supplied 2. Including when external clock is supplied
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Remark x: Don't care
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CHAPTER 24 RESET FUNCTION 24.1 Reset Function
CHAPTER 24 RESET FUNCTION
RESET Internal Reset Signal Port Pin
Delay Delay Hi-Z
X1 Normal Operation
Figure 24-2. Timing of Reset Input by RESET Input
Figure 24-3. Timing of Reset due to Watchdog Timer Overflow
Figure 24-4. Timing of Reset Input in STOP Mode by RESET Input
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CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions
25.2 ROM Correction Configuration
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CHAPTER 25 ROM CORRECTION
25.3 ROM Correction Control Registers
Note Bits 0 and 2 are read-only bits.
CHAPTER 25 ROM CORRECTION
25.4 ROM Correction Application
Figure 25-5. Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode)
EEPROM Source program
PD78058F, 78058FY EEPROM
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Figure 25-7. ROM Correction Operation
25.5 ROM Correction Example
25.6 Program Execution Flow
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25.7 Cautions on ROM Correction
CHAPTER 26
PD78P058F, 78P058FY
26.1 Memory Size Switching Register
26.2 Internal Expansion RAM Size Switching Register
26.3 PROM Programming
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26.3.2 PROM write procedure Figure 26-3. Page Program Mode Flowchart
Remark: G = Start address N = Last address of program
Figure 26-4. Page Program Mode Timing
Figure 26-5. Byte Program Mode Flowchart
Remark: G = Start address N = Last address of program
Figure 26-6. Byte Program Mode Timing
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27.1 Legends Used in Operation List
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27.2 Operation List
2. When an area except the internal high-speed RAM area is accessed.
3. Only when rp = BC, DE or HL 4. Except "r = A"
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APPENDIX A. DIFFERENCES AMONG
PD78054, 78058F, AND 780058 SUBSERIES
The major differences among the
PD78054, 78058F, and 780058 Subseries are shown in Table A-1. Table A-1. Major Differences Among
PD78054, 78058F, and 780058 Subseries (1/2)
Table A-1. Major Differences Among
PD78054, 78058F, and 780058 Subseries (2/2)
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Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS
APPENDIX B DEVELOPMENT TOOLS
Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A
B.1 Language Processing Software
B.2 PROM Programming Tool
B.3 Debugging Tool
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B.4 OS for IBM PC
B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
Based on EV-9200GC-80 (1) Package drawing (in mm)
Figure B-3. EV-9200GC-80 Footprints (For Reference Only)
F E D
HI
Reference diagram: TGK-080SDW Package dimension (unit: mm)
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C.1 Real-time OS (1/2)
Real-time OS (2/2)
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APPENDIX D REGISTER INDEX D.1 Register Index (Register Name)
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D.2 Register Index (Register Symbol)
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APPENDIX E REVISION HISTORY
Major revisions by edition and revised chapters are shown below.
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