346
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
ยต
PD78058FY SUBSERIES)
Serial Interface Channel 0 Serial Clock Selection
Serial Interface Channel 1 Serial Clock Selection
TCL33TCL32 TCL31 TCL30
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
f
XX
/2
8
f
XX
/2
9
f
XX
/2
10
f
XX
/2
11
f
XX
/2
12
MCS = 1
Setting prohibited
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.77 kHz)
f
X
/2
10
(4.88 kHz)
f
X
/2
11
(2.44 kHz)
f
X
/2
12
(1.22 kHz)
MCS = 1
Setting prohibited
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
Other than above Setting prohibited
TCL37TCL36 TCL35 TCL34
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
f
XX
/2
f
XX
/2
2
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
f
XX
/2
8
MCS = 1
Setting prohibited
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
MCS = 0
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
Other than above Setting prohibited
65432107
Symbol
TCL3 TCL37TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R/W
Address After Reset R/W
MCS = 0
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.77 kHz)
f
X
/2
10
(4.88 kHz)
f
X
/2
11
(2.44 kHz)
f
X
/2
12
(1.22 kHz)
f
X
/2
13
(0.61 kHz)
f
XX
/2
f
XX
/2
2
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
f
XX
/2
8
MCS = 0
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
f
X
/2
9
(9.8 kHz)
Serial Clock in I
2
C Bus Mode Serial Clock in 2-Wire or 3-Wire
Serial I/O Mode
Figure 17-3. Timer Clock Select Register 3 FormatCaution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fXX : Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.