NEC 7.3 Clock Generator Control Register

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CHAPTER 7 CLOCK GENERATOR
7.3 Clock Generator Control Register
The clock generator is controlled by the following two registers:
• Processor clock control register (PCC)
• Oscillation mode selection register (OSMS)
(1) Processor clock control register (PCC)
The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/
stop and subsystem clock oscillator internal feedback resistor.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Figure 7-2. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback resistor
XT1 XT2