5.2 Address Map | 36 |
5.2.1 Data FIFO Register (base + 0) | 37 |
5.2.2 Scan List Queue Register (base + 1) | 39 |
5.2.3 Status Register (base + 2) | 44 |
5.2.4 Digital I/O Register | 45 |
5.2.5 Pacer Clock (base + 4, + 5, + 6) | 46 |
5.2.6 Command Register (base + 7) | 47 |
5.2.7 D/A Data Port (base + 8, base + 9) | 49 |
5.2.8 Timer/Counter Port (base + 10, base + 11) | 51 |
5.2.9 Auxiliary Control Register (base + 15) | 53 |
5.2.10 Auxiliary Status Register (base + 15) | 53 |
6. Specifications | 55 |
7 |
