5.2 Address Map
The DAQP card uses eight consecutive I/O locations within the system I/O address space. The base address of the adapter is determined during hardware configuration. The eight I/O locations are used by the DAQP card as summarized in the following table.
Table
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| Address | I/O Address | Port Access | Register Description |
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| (A3A2A1A0) |
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| 0000 | base + 0 | Read/Write | Data FIFO |
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| 0001 | base + 1 | Write Only | Scan List (Queue) |
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| 0010 | base + 2 | Write | Control Register |
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| Read | Status Register |
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| Write | Digital Output Register |
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| 0011 | base + 3 |
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| Read | Digital Input Register |
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| 0100 | base + 4 | Write Only | Pacer Clock, low byte |
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| 0101 | base + 5 | Write Only | Pacer Clock, middle byte |
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| 0110 | base + 6 | Write Only | Pacer Clock, high byte |
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| 0111 | base + 7 | Write Only | Command Register |
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| 1000 - 1001 | base + 8, 9 | Write Only | D/A port |
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| 1010 - 1011 | base + 10, 11 | Write | Timer port |
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| Read | Timer port (read latch) |
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| 1100 - 1110 | base + 12, 13, 14 |
| reserved |
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| 1111 | base + 15 | Write | Auxiliary Control Register |
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| Read | Auxiliary Status Register |
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The D/A and timer port can be accessed as 16 bit I/O registers and with 8 bit I/O instructions. The remaining registers are 8 bits. Each is discussed in detail in the following sections.
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