Philips DVD963SA manual AV-Board Upsampling

Electrical Diagrams DVD963SA 7. 48

AV-Board: Upsampling

1

2

3

4

5

6

7

8

9

10

11

12

13

UPSAMPLING

A

A3

A3

A3

A3

A1

A1

A6

A6

I200

I201

I202

I203

A

FR DATA

FR BCK

FR LRCK

FR MCLK

24.576M

+3V3D

+3V3D

+3V3D

Upsampling

DIG OUT

SPDIF OUT

7206-B

7206-C

7206-E

74LVC04

14

74LVC04

74LVC04

14

14

2V / div DC

2V / div DC

2V / div DC

2V / div DC

3

4

5

6

11

10

2us / div

100ns / div

10us / div

20ns / div

+3V3D

7

7

7

+5VD

B

+3V3D

2200

2201

B

7206-A

100n

100n

74LVC04

7207-D

35V 10u

14

7200

1V6 1

2

1V6

+3V3D

74AC00M

14

2213

12

74LVC157A

7

13

11

A1

3V3 1

16

2202

2203

Upsampling

G1

2204

VCC

+3V3D

7

15

8

100n

100n

EN

GND

100n

7205

16

7204

74LVC161

C

0V

2

I200

74LVC161

16

2

CP

VCC

C

1~ MUX

4

0V

2

CP

VCC

0V

3

1

MR_

+5VD

A1

SDT1

1

I201

1

MR_

+5VD

+5VD

1V6 5

+5VD

9

PE_

0V3

7

9

PE_

7207-A

BINARY COUNTER

7207-C

A1

BCLK

0V7 6

3

D0

BINARY COUNTER

Q0

14

1V6

3

D0

PARALLEL LOAD

Q0

14

74AC00M

14

I202

PARALLEL LOAD

4

D1

Q1

13

1V8

1

3

I212

74AC00M 14

1V6 11

9

1V6

4

D1

Q1

13

3V3

2

9

8

A1

LRCLK

1V6 10

5

D2

Q2

12

1V6

2V4

10

I203

5

D2

Q2

12

1V8

7

A1

24.576M

1V6 14

6

D3

Q3

11

7

D

12

1V6

6

D3

Q3

11

D

1V6 13

A1

MCLK1

10

CET

+5VD

10

CET

TC

15

I220

+5VD

TC

15

7

5V

0V

7

6

CEP

GND

CEP

GND

8

+5VD

14

7

8

12.88M

74AC00M

7207-B

I214

+3V3D

1V

A1

192K_96K

3200

I222

192k

12.288M

7206-D

4

5

E

27K

74LVC04

14

E

3V3

9

8

0V

0V

7221

+3V3D

192k

7

I222

3201

3202

I215

I216

BC847B

500mV / div DC

2V / div DC

2V / div DC

+5VD

+3V3D

1R

1R

3V

4K7

200ns / div

2us / div

50ns / div

2205

10u

I217

I218

10u

3212

2206

7202

F

F

2207

2208

74LVC245

+3V3D

100n

100n

2209

I219

19

20

7206-F

G3

VCC

100n

74LVC04

1

10

14

3204

4K7

7201

3EN1

GND

1V6

12

13 1V6

24.576M

A1

3EN2

AD1895

7

22

7

10u

I207

13

RESET_

VDD-IO

VDD-CORE

2

18

2210

14

MUTE-I

1

SDATA-O

23

0V

G

A1

SDT1

0V

4

SDATA-I

2

G

FIFO

FSOUT

SCLK-O

25

1V6 3

17

1V6

A1

BCLK

0V7

5

SCLK-I

FS IN

SERIAL INPUT

LRCLK-O

24

1V6 4

16

1V6

LRCLK

1V6

6

LRCLK-I

A1

SERIAL OUTPUT

5

15

5V

10

SMODE-IN-0

TDM-I

20

6

14

7203

11

SMODE-IN-1

AK4103VF

SMODE-O-0

19

7

13

12

SMODE-IN-2

1

24

DIG

FIR

SMODE-O-1

18

8

12

V1

U1

I223

3205

A1

Upsampling

3V3 9

BYPASS

PLL

FIL

2

23

9

11

3206

TRANS

DIF2

+5VD

H

5V 3

22

2K2

H

A1

AD1895_CLK

1V6 2

MCLK-I

WLNGTH-O-0 17

+5VD

PDN

DIF1

ROM

2K2

4

21

3207

I208

5V

26

MMODE-0

WLNGTH-O-1

16

MCLK

DIF0

0V 5

20 1V4

I224

3208

2K2

27K I209 0V

SDTI

TXP

A1

192K_96K

27

MMODE-1

3203

7220

3213

2K2

28

MMODE-2 CLOCK

DIV

MUTE-O

15

1V6 6

BICK

TXN

19

330R

1V6 7

18

+5VD

BC847B

NC

MCLK-O

DGND

LRCK

VSS

8

17

100n

1

3

8

21

FS0CSN

VDD

2211

5V

+5VD

3V 9

FS1CDTI

CKS1

16

I

3210

10

15

I

A1

SPDIF_MUTE

3215

7222

+5VD

3211

2K2

FS2CCLK

CKS0

27K

BC847B

11

FS3CDTO

BLS

14

2K2

10u

I225

3214

12

C1

ANS

13

+5VD

* RESERVED

2K2

2212

V DC Vtg measured in STOP-MODE

BARE BOARD : 3139-243-30533

CL 26532105_006.eps

020902

1

2

3

4

5

6

7

8

9

10

11

12

13

2200 B6

2201 B13

2202 C4

2203 C11

2204 C8

2205 F4

2206 F5

2207 F4

2208 F5

2209 F8

2210 G3

2211 I12

2212 I10

2213 B4

3200 E5

3201 E4

3202 E5

3203 H2

3204 F3

3205 H13

3206 H9

3207 H13

3208 H12

3210 I9

3211 I9

3212 F7

3213 H3

3214 I12

3215 I2

7200 B4

7201 F4

7202 F7

7203 G10

7204 C7

7205 C10

7206-A B6

7206-B A7

7206-C A8

7206-D E11

7206-E A10

7206-F F13

7207-A C12

7207-B E12

7207-C C13

7207-D B12

7220 H2

7221 E7

7222 I3

I200 C4

I201 C4

I202 D4

I203 D4

I207 G3

I208 H3

I209 H2

I212 D12

I214 E6

I215 E4

I216 E5

I217 F4

I218 F5

I219 F7

I220 D13

I222 E13

I223 H12

I224 H12

I225 I12