Pico E-15 | Pico Communications instruction

Pico Computing

Pico E-15

Hardware Technical

Reference

Release: 1.01

For Hardware Revision: D

www.picocomputing.com	Pico Computing
(206) 283-2178	150 Nickerson Street. Suite 311
	Seattle, WA 98109

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Pico Communications manual Pico E-15, Release For Hardware Revision D

Contents

Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference Datasheet Standard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Minimum Nominal Maximum Pico E-15 Electrical Specification Field Programmable Gate Array PPC405x3 Processor Introduction PowerPC Processor Cpld Resources Xilinx Cpld Website Cpld TurboLoader Flash Memory DDR2 Sdram Memory RAM Parameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter Information Electrical Specifications Minimum Nominal Maximum Temperature Sensor Sleep Controller Ethernet Resources Tri-Mode Ethernet Interface HI-Z Digital Peripheral Interface High Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Composite Mode Video Digitizer External Connections Svideo ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 Homepage CardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing FCI Appendix B CardBus Connector Information CardBus Interface Schematic Pcicpar CardBus Connector Pinout PCICAD17 Fpga Pinout Appendix C Fpga Pinout CAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld Pinout PSoC Pinout Appendix E PSoC Pinout Standard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices