Pico Communications E-15 manual

www.picocomputing.com Pico Computing

(206) 283-2178 150 Nickerson Street. Suite 311

Seattle, WA 98109

Pico

PicoPico

Pico Computing

Computing Computing

Computing

Pico E-15

Hardware Technical

Reference

Release: 1.01

For Hardware Revision: D

Contents

Main Pico PicoPico Pico Computing Computing Computing Computing Pico E-15 Hardware Technical Reference Page Product Overview: Pico E-15 Quick Reference Datasheet FEATURES FPGA FEATURES APPLICATIONS Standard Part Numbers Standard Part Number A Military version is available which includes: System Architecture Pico E-15 Electrical Specification Field Programmable Gate Array FPGA Resources: Free FPGA Cores http://www.opencores.org Encryption Cores http://www.openciphers.org Virtex-4 Website http://www.xilinx.com/virtex4 PowerPC Processor PPC405x3 Processor Introduction: CPLD TurboLoader Flash Memory DDR2 SDRAM Memory Virtex-4 FPGA RAM MSBs RAM LSBs RAM Timing and Parameter Information Parameter Value EDK Value 133 MHz EDK Value 333 MHz Temperature Sensor Sleep Controller Tri-Mode Ethernet Interface Ethernet Resources: Digital Peripheral Interface High Speed Analog to Digital Converters Page Page High Speed Digital to Analog Converters Page Video Digitizer CardBus / Digital Bus Interface JTAG Debug Interface EthernetTurbo Loader Device Instruction register bit length PSoC Debug Interface Appendix A Peripheral I/O Connector Information Connector Information Description Brand Part Number Mating Connector Hirose NX-32TA-CV1(50) Peripheral I/O Connector Pinout Page Appendix B CardBus Connector Information Connector Information Page (206) 283-2178 150 Nickerson Street. Suite 311 Seattle, WA 98109 CardBus Connector Pinout Page Appendix C FPGA Pinout FPGA Pinout Page Page Page Page Page Page Appendix D CPLD Pinout CPLD Pinout Appendix E PSoC Pinout PSoC Pinout Appendix F Standard Part Number Listing Standard Part Number Listing Appendix G Errata Appendix H FPGA Performance Enhancements Revision History Legal Notices