Flash Memory | Pico Communications E-15 instruction

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Flash Memory

The Pico E-15 comes equipped with at least 64MB of Flash ROM. The Flash ROM is divided into 512 sectors that can be erased independently. Most of the space on the ROM is reserved for the user.

The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address bus. At all other times the FPGA is in control of the address bus.

The Flash ROM has a simple, open file system which allows the user to store FPGA images, ELF binary files, or other data. The primary image is used to boot the FPGA initially, and the backup image is only invoked if the primary image fails to load correctly. Executable files are in ELF format and are loaded by a loader within the secondary image. The primary image will either load the secondary image or pause for the PC to access and manage the file system.

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Pico Communications E-15 manual Flash Memory

Contents

Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference Datasheet Military version is available which includes Standard Part NumbersStandard Part Number System Architecture Minimum Nominal Maximum Pico E-15 Electrical Specification Field Programmable Gate Array PPC405x3 Processor Introduction PowerPC Processor Cpld Resources Xilinx Cpld Website Cpld TurboLoader Flash Memory DDR2 Sdram Memory RAM Parameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter Information Electrical Specifications Minimum Nominal Maximum Temperature Sensor Sleep Controller Ethernet Resources Tri-Mode Ethernet Interface HI-Z Digital Peripheral Interface High Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Resources TVP5150AM1 Homepage Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video Digitizer Pcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing FCI Appendix B CardBus Connector Information CardBus Interface Schematic Pcicpar CardBus Connector Pinout PCICAD17 Fpga Pinout Appendix C Fpga Pinout CAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld Pinout PSoC Pinout Appendix E PSoC Pinout Device Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices