Pico Communications E-15 specification

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Contents:
Product Overview	3
Quick Reference Datasheet	4
Standard Part Numbers	5
System Architecture	6
Electrical Specification	7
Features
Field Programmable Gate Array	8
PowerPC™ Processor	9
CPLD TurboLoader	10
Flash Memory	11
DDR2 SDRAM Memory	12
Temperature Sensor	14
I/O Interfaces
Sleep Controller	15
Tri-Mode Ethernet Interface	16
Digital Peripheral Interface	17
High Speed Analog to Digital Converters	18
High Speed Digital to Analog Converters	21
Video Digitizer	23
CardBus / Digital Bus Interface	24
JTAG Debug Interface	25
PSoC Debug Interface	26
Appendices
A – Peripheral I/O Connector Information	27
B – CardBus Connector Information	28
C – FPGA Pinout	29
D – CPLD Pinout	33
E – PSoC Pinout	40
F – Standard Part Number Listing	41
G – Errata	43
H – FPGA Performance Enhancements	44
Revision History	45
Legal Notices	46

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Pico Communications E-15 manual

Contents

Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO Connectivity Military version is available which includes Standard Part NumbersStandard Part Number System Architecture Pico E-15 Electrical Specification Minimum Nominal Maximum Field Programmable Gate Array PowerPC Processor PPC405x3 Processor Introduction Cpld TurboLoader Cpld Resources Xilinx Cpld Website Flash Memory RAM DDR2 Sdram Memory RAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHz Temperature Sensor Electrical Specifications Minimum Nominal Maximum Sleep Controller Tri-Mode Ethernet Interface Ethernet Resources Digital Peripheral Interface HI-Z High Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video Digitizer Resources TVP5150AM1 Homepage Pcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing Appendix B CardBus Connector Information FCI CardBus Interface Schematic CardBus Connector Pinout Pcicpar PCICAD17 Appendix C Fpga Pinout Fpga Pinout CAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld Pinout Appendix E PSoC Pinout PSoC Pinout Device Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices