Temperature Sensor | Pico Communications E-15 guide

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Temperature Sensor

The Pico E-15 contains one temperature sensor that directly senses the die temperature of the Virex-4 FPGA. The digital interface of the remote temperature sensing chip is connected to the Cypress PSoC. If an overtemperature condition occurs, the PSoC will shutdown the FPGA until the temperature has dropped sufficiently below the shutdown threshold.

The setpoints of the temperature shutdown circuit can be reprogrammed via the PSoC debug cable.

Electrical Specifications	Minimum	Nominal	Maximum
Temperature Sensing Range	-55°C		125°C
Resolution		0.0625°C
Accuracy	+/- 2.4°C	+/- 1.0°C	+/- 0.0°C

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Pico Communications E-15 manual Temperature Sensor, Electrical Specifications Minimum Nominal Maximum

Contents

Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO Connectivity Military version is available which includes Standard Part NumbersStandard Part Number System Architecture Pico E-15 Electrical Specification Minimum Nominal Maximum Field Programmable Gate Array PowerPC Processor PPC405x3 Processor Introduction Cpld TurboLoader Cpld Resources Xilinx Cpld Website Flash Memory RAM DDR2 Sdram Memory RAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHz Temperature Sensor Electrical Specifications Minimum Nominal Maximum Sleep Controller Tri-Mode Ethernet Interface Ethernet Resources Digital Peripheral Interface HI-Z High Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video Digitizer Resources TVP5150AM1 Homepage Pcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing Appendix B CardBus Connector Information FCI CardBus Interface Schematic CardBus Connector Pinout Pcicpar PCICAD17 Appendix C Fpga Pinout Fpga Pinout CAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld Pinout Appendix E PSoC Pinout PSoC Pinout Device Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices