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JTAG Debug Interface
The Pico
Some JTAG programs require the length of the instruction register (IR). The IR length is listed below for all devices in the JTAG chain. The FPGA IR length changes depending on how many PowerPCs are internally connected to the JTAG chain in the FPGA.
Device
FPGA
TurboLoader
Ethernet PHY
Instruction register bit length
6,10 or 14 (Depends on PPC Configuration)
8
8
TDI
FPGA
PowerPC
Turbo Loader
Ethernet
TDO
IR= 10 | IR= 8 | IR= 8 |
The Primary Image in the Flash ROM contains an embedded JTAG diagnostic port. This allows a user in Windows or Linux to debug software without an external JTAG cable. The internal JTAG diagnostic loopback looks just like a Parallel Port JTAG diagnostic cable when used with the Pico
The external JTAG interface uses 1.8V logic.
Pico | www.picocomputing.com | Pico Computing |
| (206) | 150 Nickerson Street. Suite 311 |
|
| Seattle, WA 98109 |