Pico Communications E-15 specification

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DAC Low Frequency Maximum Amplitude (50 Ohm Load)

DAC High Frequency Maximum Amplitude (50 Ohm Load)

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Pico Communications E-15 manual

Contents

Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO Connectivity Standard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Pico E-15 Electrical Specification Minimum Nominal Maximum Field Programmable Gate Array PowerPC Processor PPC405x3 Processor Introduction Cpld TurboLoader Cpld Resources Xilinx Cpld Website Flash Memory RAM DDR2 Sdram Memory RAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHz Temperature Sensor Electrical Specifications Minimum Nominal Maximum Sleep Controller Tri-Mode Ethernet Interface Ethernet Resources Digital Peripheral Interface HI-Z High Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video Digitizer Resources TVP5150AM1 Homepage CardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing Appendix B CardBus Connector Information FCI CardBus Interface Schematic CardBus Connector Pinout Pcicpar PCICAD17 Appendix C Fpga Pinout Fpga Pinout CAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld Pinout Appendix E PSoC Pinout PSoC Pinout Standard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices