Samsung CLP-300 XSG manual Main Board4/15, Vclk

Main Board(4/15)

Schematic Diagram

A

B

C

D

E

F

1 2 3 4 5

C211

C210

C129

15pF

XI_VCLK

DGND

15pF

OSC5

15pF

OSC2

ATS-49/U,12MHz,50ppm

F1

+3.3V

C128

15pF

XO_VCLK

+3.3V

STS104B

DGND

ATS-49/U,12MHz,50ppm

U12

1

3

R190

1

XIN/CLKIN

XOUT

8

C194

2

2

7

0

VSS

VDD

100nF

[ VCLK ]

3

S1

FRSEL

6

DGND

4

S0

SSCLK

5

R88

33

XI_MCLK

R189

NR114

CY25811

C178

0

0

15pF

C312

22pF

DGND

DGND

DGND

+5V

S0

S1

U19

1

2

3

0%

N.C

N.C

F2

NC1

NC2

NC3

STS104B

0.4%

LOW

N.C

1

3

7

PVIN

SW

6

0.5%

1

0

2

R115

8

SVIN

SFB

5

1.1%

N.C

0

10

10

SHDN

VSET

11

1.3%

0

0

4

12

[ SYSTEM CLOCK ]

SGND

PSET

100nF

10uF

NC4

PGND

C234

C244

9

13

MVPG31

DGND

nRESET

+3.3V

CLX-3160FN ONLY

+3.3V

Vb

R170

R121

0

C308

1K

Q11

+3.3V

R172

47uF

U25

100

KSC1623-Y R142 300

3

1

16V

Q9

1

NR6 30K

1

3

KSB1151-Y

3

Vout

2

Vin

2

DGND

2

R151

Vss

C277

C302

470K

+5V

100nF

XC61FN3112MR

1nF

D27

RB420D T147

R152

5.6K

1

2

Q12

DGND

KSA1182-Y

R161

DGND

DGND

3

56

R162

56

VBIN

[ SYSTEM RESET ]

B 1 1 B 2 3 4 5

			6			7		8
										A
C165		22pF	XI_RTC					LED1 SLS-NNGA102TS		+3.3V
					TEST_LED3		R175	5.1K
	OSC3
			MC-306,32.768KHz
C155		22pF	XO_RTC
DGND
			[ RTC ]
										B
			+1.2V	+5V					+3.3V
					F3		U24
					STS104B		LD1117DT33C
L9	2.2uH			1	3		3 IN	OUT 2
					2			GND
						C303		1	C255	C
R105 31.6K,1%							C301		100uF
						10uF
							100nF		16V
			C243			16V
			22uF
R109 280K,1%
					DGND
										D

L8

L5

DGND FGND

E

3301-000325R3225_BEAD

	Engineer K.C.LEE		Digtal Printing Division
	Drawn by		R&D 5
	R&D CHK S.D.AN	TITLE:		Size	F
				A3
	DOC CTRL CHK	CLP-300(N)/CLX-3160N(FN)
	MFG ENGR CHK		Main_V0.11
		Clock & Power On Reset		4/15
6	7		8

11-4Service Manual

Samsung Electronics

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