©Copyright 2000-2007 SD Card Association

SDIO Simplified Specification Version 2.00

Field

Type

Description

Bus Width

R/W

Defines the data bus width (’00’=1-bit or’10’=4-bit bus) to be used for data transfer. All

1:0

 

Full-Speed SDIO cards support both 1 and 4-bit bus. A Low-Speed SDIO card’s

 

 

support of 4-bit bus is optional. On reset or power-on these bits are cleared to 00.

CD Disable

R/W

Connect[0]/Disconnect[1] the 10K-90K ohm pull-up resistor on CD/DAT[3] (pin 1) of

 

 

the card. The pull-up may be used for card detection. This bit is cleared to 0 on

 

 

power-on (connected). Its state is not affected by a reset command.

SCSI

R/O

Support Continuous SPI interrupt. This read-only bit is set to indicate that this SDIO

 

 

card supports the assertion of interrupts in the SPI mode at any time, irrespective of

 

 

the status of the card select (CS) line. If this bit is zero, then this SDIO card can only

 

 

assert the interrupt line in the SPI mode when the CS line is asserted. This bit signals

 

 

the capability of all functions in the SDIO card.

ECSI

R/W

Enable Continuous SPI Interrupt. If the SCSI bit is set, then this R/W bit is used to

 

 

allow the SDIO card to assert the interrupt line in the SPI mode at any time,

 

 

irrespective of the state of the CS line. This bit is cleared to zero on reset or power-up.

 

 

If the SCSI bit is clear, this bit shall be read only and set to zero. This bit controls the

 

 

assertion of interrupts in the SPI mode for all functions in the SDIO card.

SDC

R/O

Card Supports Direct Commands during data transfer. This bit applies only to the SD

 

 

modes, it does not apply to SPI mode. This flag bit reports the SDIO card’s ability to

 

 

execute CMD52 while data transfer is in progress. If this bit is set, all I/O functions

 

 

shall accept and execute the CMD52 while data transfer is underway on the DAT[x]

 

 

lines. Also, any memory in a combo card shall allow the CMD52 to execute while it is

 

 

transferring data. Since the CMD52 does not use the DAT[x] lines, it is possible to

 

 

execute while data transfer to a different address on the card is underway. CMD52 is

 

 

described in 5.1. In any case, SD or SPI mode, if an error occurs during data transfer

 

 

the SDIO card shall accept CMD52 to allow I/O abort and reset regardless of this bit

 

 

value. If the card supports suspend/resume then it shall also support this bit.

SMB

R/O

Card Supports Multi-Block. This flag bit reports the SDIO card’s ability to execute the

 

 

IO_RW_EXTENDED command (CMD53) in the block mode. If this bit is set, all I/O

 

 

functions (0-7) shall accept and execute CMD53 with the optional block mode bit set.

 

 

The IO_RW_EXTENDED command is described in 5.3

SRW

R/O

Card Supports Read Wait. This bit applies only to the SD modes, it does not apply to

 

 

SPI mode. This flag bit reports the SDIO card’s ability to support the Read Wait

 

 

Control (RWC) operation. If set, all functions on the card are able to accept the wait

 

 

signal on DAT[2]. RWC operation is described in section 6.5. Any card that supports

 

 

Suspend/Resume shall also support Read Wait

SBS

R/O

Card supports Suspend/Resume. This bit applies only to the SD modes, it does not

 

 

apply to SPI mode. This flag bit reports the SDIO card’s ability to Suspend and

 

 

Resume operations at the request of the host. If this bit is set, all functions except 0

 

 

shall accept a request to suspend operations and resume under host control.

 

 

Suspend/Resume operation is described in 6.4. If this bit is 0, registers (0x0C-0x0F)

 

 

shall not be supported.

S4MI

R/O

Supports interrupt between blocks of data in 4-bit SD mode. This flag bit reports the

 

 

SDIO card’s ability to generate interrupts during a 4-bit multi-block data transfer. If

 

 

this bit is 0, then the SDIO card is not able to signal an interrupt during a multi-block

 

 

data transfer in 4-bit mode. In this case, the interrupt is not signaled until after the

 

 

data transfer is complete. If this bit is 1, then the SDIO card is able to signal an

 

 

interrupt between blocks while data transfer is in progress. This operation is

 

 

described in 8.1.4 Note, even if a card does not support the interrupt during 4-bit

 

 

block transfer (S4MI=0), the card may signal interrupts during all other Interrupt

 

 

Periods while the interrupt is enabled (IENx=1).

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SDI Technologies SDIO Card manual Scsi