SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T Architectural Overview

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Architectural Overview

Symbol

Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right).

As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in an FPGA design

essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other

32-bit processors supported by Altium Designer.

The third interface provides connection to the physical LH79520 itself. More specifically, it caters for:

• Data and Address bus signals to/from the LH79520's External Bus Interface (EBI)

• Control signals from the LH79520's Static Memory Controller (SMC)

• Clock, Reset and Interrupt signals.

The corresponding signals from the physical LH79520 must be hardwired to the desired pins of the physical FPGA device. To

wire from the ARM720T_LH79520 Wishbone wrapper to the physical pins of the FPGA device requires the use of the relevant

port-plugin component (PROCESSOR_ARM7_LH79520). For more information, refer to the section Placing an

ARM720T_LH79520 in an FPGA design.

CR0162 (v2.0) March 10, 2008 5

Contents

Main ARM720T_LH79520 Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Summary Features Available Devices RISC Processor Background History 2 CR0162 (v2.0) March 10, 2008 Soft FPGA Processors Why use Soft Processors? The ARM720T_LH79520 Wishbone Bus Interfaces Wishbone OpenBUS Processor Wrappers Processor Abstraction System Design Migration Architectural Overview Symbol Pin Description 6 CR0162 (v2.0) March 10, 2008 Page Configuring the Processor 8 CR0162 (v2.0) March 10, 2008 Page Memory & I/O Management Defining the Memory Map 10 CR0162 (v2.0) March 10, 2008 Building the Bridge between the Hardware and Software Page Place Interconnect Division of Memory Space Internal Memory External Memory Peripheral I/O Data Organization Words, Half-Words and Bytes Physical Interface to Memory and Peripherals Peripheral I/O 16 CR0162 (v2.0) March 10, 2008 Hardware Description Clocking Reset Interrupts Wishbone Communications Writing to a Slave Wishbone Peripheral Device Reading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory Device Reading from a Slave Wishbone Memory Device Wishbone Timing Placing an ARM720T_LH79520 in an FPGA design Design using a Schematic only 20 CR0162 (v2.0) March 10, 2008 Design Featuring an OpenBus System Facilitating Communications Additional 'Soft' Devices in Your Design Enabling the Soft Devices JTAG Chain Downloading Your Design On-Chip Debugging Accessing the Debug Environment Page Page Page Instruction Set Revision History