Sun Microsystems X4240, X4440 Initializes NUM-LOCK status and programs the KBD typematic rate

TABLE A-2	POST Code Checkpoints (Continued)
Post Code	Description
60	Initializes NUM-LOCK status and programs the KBD typematic rate.
75	Initialize Int-13 and prepare for IPL detection.
78	Initializes IPL devices controlled by BIOS and option ROMs.
7A	Initializes remaining option ROMs.
7C	Generate and write contents of ESCD in NVRam.
84	Log errors encountered during POST.
85	Displays errors to the user and gets the user response for error.
87	Execute BIOS setup if needed/requested.
8C	After all device initialization is done, program any user selectable parameters relating to
	NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM
	cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during
	Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on
	setup questions. Get the DRAM scrub limits from each node.
8D	Build ACPI tables (if ACPI is supported).
8E	Program the peripheral parameters. Enable/Disable NMI as selected.
90	Late POST initialization of system management interrupt.
A0	Check boot password if installed.
A1	Clean-up work needed before booting to OS.
A2	Takes care of runtime image preparation for different BIOS modules. Fills the free area in
	F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the
	runtime language module. Disables the system configuration display if needed.
A4	Initialize runtime language module.
A7	Displays the system configuration screen if enabled. Initializes the CPUs before boot,
	which includes the programming of the MTRRs.
A8	Prepare CPU for OS boot including final MTRR values.
A9	Wait for user input at configuration display if needed.
AA	Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB	Prepare BBS for Int 19 boot.
AC	Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just
	before giving control to runtime code booting to OS. Program the system BIOS (0F0000h

shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.

Appendix A Event Logs and POST Codes 35