Registers
5.7Set Rising Edge Interrupt Register (SET_RIS_TRIG)
The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the rising edge of GPn. RIS_TRIG is not directly accessible by the CPU; it must be configured using the GPIO set rising trigger and clear rising trigger registers.
The GPIO set rising trigger register (SET_RIS_TRIG) is shown in Figure 9 and described in Table 9. Writing a 1 to a bit of SET_RIS_TRIG sets the corresponding bit in RIS_TRIG. Writing a 0 has no effect. Reading SET_RIS_TRIG returns the value in RIS_TRIG.
Figure 9. | Set Rising Edge Interrupt Register (SET_RIS_TRIG) |
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31 |
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| 16 |
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| Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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SETRIS15 | SETRIS14 | SETRIS13 | SETRIS12 | SETRIS11 | SETRIS10 | SETRIS9 | SETRIS8 |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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SETRIS7 | SETRIS6 | SETRIS5 | SETRIS4 | SETRIS3 | SETRIS2 | SETRIS1 | SETRIS0 |
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Legend: R = Read only; R/W = Read/Write; |
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Table 9. | Set Rising Edge Interrupt Register (SET_RIS_TRIG) Field Descriptions | ||
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Bit | Field | Value | Description |
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31−16 | Reserved | 0 | Reserved. The reserved bit location is always read as 0. A value written to |
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| this field has no effect. |
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15−0 | SETRISn |
| Writing a 1 enables the rising edge detection for the corresponding GPn pin. |
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| Reading this register returns the state of the RIS_TRIG register. |
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| 0 | No effect |
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| 1 | Sets the corresponding bit in RIS_TRIG |
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22 | SPRU724 |