Registers
5.1Interrupt Per-Bank Enable Register (BINTEN)
To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown in Figure 3 and described in Table 3.
Figure 3. | Interrupt |
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31 |
| 1 | 0 |
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| Reserved |
| EN |
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Legend: R = Read only; R/W = Read/Write; |
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Table 3. | Interrupt | ||
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Bit | Field | Value | Description |
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31−1 | Reserved | 0 | Reserved. The reserved bit location is always read as 0. A value written to |
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| this field has no effect. |
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0 | EN |
| Enables all GPIO pins as interrupt sources to the DSP CPU. |
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| 0 | Disables GPIO interrupts |
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| 1 | Enables GPIO interrupts |
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16 | SPRU724 |
